Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ce76f9fd authored by Jassi Brar's avatar Jassi Brar Committed by Mark Brown
Browse files

ASoC: S3C2412: I2S: Debug IMS field



The IMS field of s3c2412/13 is essentially the same as that of s3c64xx.
That is, the IISMOD[11] bit decides Master/Slave mode and IISMOD[10] bit
selects source clock for signal generation.
For that reason, remove improper defines for IISMOD[11:10] field mask
and define two 1bit fields that can be set independent of each other.
As a consequence, corresponding fields for PLAT_S3C64XX too get to use
these new defines.

Signed-off-by: default avatarJassi Brar <jassi.brar@samsung.com>
Acked-by: default avatarBen Dooks <ben-linux@fluff.org>
Acked-by: default avatarLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent b720d562
Loading
Loading
Loading
Loading
+2 −4
Original line number Original line Diff line number Diff line
@@ -76,10 +76,8 @@
#define S3C64XX_IISMOD_IMS_PCLK		(0 << 10)
#define S3C64XX_IISMOD_IMS_PCLK		(0 << 10)
#define S3C64XX_IISMOD_IMS_SYSMUX	(1 << 10)
#define S3C64XX_IISMOD_IMS_SYSMUX	(1 << 10)


#define S3C2412_IISMOD_MASTER_INTERNAL	(0 << 10)
#define S3C2412_IISMOD_IMS_SYSMUX	(1 << 10)
#define S3C2412_IISMOD_MASTER_EXTERNAL	(1 << 10)
#define S3C2412_IISMOD_SLAVE		(1 << 11)
#define S3C2412_IISMOD_SLAVE		(2 << 10)
#define S3C2412_IISMOD_MASTER_MASK	(3 << 10)
#define S3C2412_IISMOD_MODE_TXONLY	(0 << 8)
#define S3C2412_IISMOD_MODE_TXONLY	(0 << 8)
#define S3C2412_IISMOD_MODE_RXONLY	(1 << 8)
#define S3C2412_IISMOD_MODE_RXONLY	(1 << 8)
#define S3C2412_IISMOD_MODE_TXRX	(2 << 8)
#define S3C2412_IISMOD_MODE_TXRX	(2 << 8)
+2 −23
Original line number Original line Diff line number Diff line
@@ -265,35 +265,14 @@ static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
	iismod = readl(i2s->regs + S3C2412_IISMOD);
	iismod = readl(i2s->regs + S3C2412_IISMOD);
	pr_debug("hw_params r: IISMOD: %x \n", iismod);
	pr_debug("hw_params r: IISMOD: %x \n", iismod);


#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
#define IISMOD_MASTER_MASK S3C2412_IISMOD_MASTER_MASK
#define IISMOD_SLAVE S3C2412_IISMOD_SLAVE
#define IISMOD_MASTER S3C2412_IISMOD_MASTER_INTERNAL
#endif

#if defined(CONFIG_PLAT_S3C64XX)
/* From Rev1.1 datasheet, we have two master and two slave modes:
 * IMS[11:10]:
 *	00 = master mode, fed from PCLK
 *	01 = master mode, fed from CLKAUDIO
 *	10 = slave mode, using PCLK
 *	11 = slave mode, using I2SCLK
 */
#define IISMOD_MASTER_MASK (1 << 11)
#define IISMOD_SLAVE (1 << 11)
#define IISMOD_MASTER (0 << 11)
#endif

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBM_CFM:
	case SND_SOC_DAIFMT_CBM_CFM:
		i2s->master = 0;
		i2s->master = 0;
		iismod &= ~IISMOD_MASTER_MASK;
		iismod |= S3C2412_IISMOD_SLAVE;
		iismod |= IISMOD_SLAVE;
		break;
		break;
	case SND_SOC_DAIFMT_CBS_CFS:
	case SND_SOC_DAIFMT_CBS_CFS:
		i2s->master = 1;
		i2s->master = 1;
		iismod &= ~IISMOD_MASTER_MASK;
		iismod &= ~S3C2412_IISMOD_SLAVE;
		iismod |= IISMOD_MASTER;
		break;
		break;
	default:
	default:
		pr_err("unknwon master/slave format\n");
		pr_err("unknwon master/slave format\n");
+2 −6
Original line number Original line Diff line number Diff line
@@ -78,14 +78,10 @@ static int s3c2412_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,


	switch (clk_id) {
	switch (clk_id) {
	case S3C2412_CLKSRC_PCLK:
	case S3C2412_CLKSRC_PCLK:
		s3c2412_i2s.master = 1;
		iismod &= ~S3C2412_IISMOD_IMS_SYSMUX;
		iismod &= ~S3C2412_IISMOD_MASTER_MASK;
		iismod |= S3C2412_IISMOD_MASTER_INTERNAL;
		break;
		break;
	case S3C2412_CLKSRC_I2SCLK:
	case S3C2412_CLKSRC_I2SCLK:
		s3c2412_i2s.master = 0;
		iismod |= S3C2412_IISMOD_IMS_SYSMUX;
		iismod &= ~S3C2412_IISMOD_MASTER_MASK;
		iismod |= S3C2412_IISMOD_MASTER_EXTERNAL;
		break;
		break;
	default:
	default:
		return -EINVAL;
		return -EINVAL;