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Commit ce6786fb authored by Patrick Daly's avatar Patrick Daly
Browse files

iommu: io-pgtable-arm: Support DOMAIN_ATTRIBUTE_USE_UPSTREAM_HINT 



Implement this new attribute. It will be used on the skunk target for
allowing smmu clients to set the bus attributes required to use system
cache on behalf of the iommu page table walker.

Change-Id: I8d09719696d878da42d0a480a002373db5bf24e4
Signed-off-by: default avatarPatrick Daly <pdaly@codeaurora.org>
parent 0b37c5a8

drivers/iommu/arm-smmu.c

+20 −0
Original line number Diff line number Diff line
@@ -1575,6 +1575,7 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, 
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);

	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;

	bool is_fast = smmu_domain->attributes & (1 << DOMAIN_ATTR_FAST);

	unsigned long quirks = 0;

	bool dynamic;



	mutex_lock(&smmu_domain->init_mutex);
@@ -1681,6 +1682,8 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, 
	if (is_fast)

		fmt = ARM_V8L_FAST;



	if (smmu_domain->attributes & (1 << DOMAIN_ATTR_USE_UPSTREAM_HINT))

		quirks |= IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT;



	/* Dynamic domains must set cbndx through domain attribute */

	if (!dynamic) {
@@ -1698,6 +1701,7 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, 
	}



	smmu_domain->pgtbl_cfg = (struct io_pgtable_cfg) {

		.quirks		= quirks,

		.pgsize_bitmap	= smmu->pgsize_bitmap,

		.ias		= ias,

		.oas		= oas,
@@ -2579,6 +2583,11 @@ static int arm_smmu_domain_get_attr(struct iommu_domain *domain, 
					& (1 << DOMAIN_ATTR_FAST));

		ret = 0;

		break;

	case DOMAIN_ATTR_USE_UPSTREAM_HINT:

		*((int *)data) = !!(smmu_domain->attributes &

				   (1 << DOMAIN_ATTR_USE_UPSTREAM_HINT));

		ret = 0;

		break;

	default:

		return -ENODEV;

	}
@@ -2706,6 +2715,17 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain, 
			smmu_domain->attributes |= 1 << DOMAIN_ATTR_FAST;

		ret = 0;

		break;

	case DOMAIN_ATTR_USE_UPSTREAM_HINT:

		/* can't be changed while attached */

		if (smmu_domain->smmu != NULL) {

			ret = -EBUSY;

			break;

		}

		if (*((int *)data))

			smmu_domain->attributes |=

				1 << DOMAIN_ATTR_USE_UPSTREAM_HINT;

		ret = 0;

		break;

	default:

		ret = -ENODEV;

	}

drivers/iommu/io-pgtable-arm.c

+4 −3
Original line number Diff line number Diff line
@@ -926,9 +926,6 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) 
	u64 reg;

	struct arm_lpae_io_pgtable *data;



	if (cfg->quirks & ~IO_PGTABLE_QUIRK_ARM_NS)

		return NULL;



	data = arm_lpae_alloc_pgtable(cfg);

	if (!data)

		return NULL;
@@ -938,6 +935,10 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) 
		reg = (ARM_LPAE_TCR_SH_OS << ARM_LPAE_TCR_SH0_SHIFT) |

			(ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) |

			(ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);

	else if (cfg->quirks && IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT)

		reg = (ARM_LPAE_TCR_SH_OS << ARM_LPAE_TCR_SH0_SHIFT) |

			(ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_IRGN0_SHIFT) |

			(ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);

	else

		reg = (ARM_LPAE_TCR_SH_OS << ARM_LPAE_TCR_SH0_SHIFT) |

			(ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_IRGN0_SHIFT) |

drivers/iommu/io-pgtable-fast.c

+8 −3
Original line number Diff line number Diff line
@@ -433,6 +433,11 @@ av8l_fast_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie) 
	cfg->pgsize_bitmap = SZ_4K;



	/* TCR */

	if (cfg->quirks && IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT)

		reg = (AV8L_FAST_TCR_SH_OS << AV8L_FAST_TCR_SH0_SHIFT) |

			(AV8L_FAST_TCR_RGN_NC << AV8L_FAST_TCR_IRGN0_SHIFT) |

			(AV8L_FAST_TCR_RGN_WBWA << AV8L_FAST_TCR_ORGN0_SHIFT);

	else

		reg = (AV8L_FAST_TCR_SH_IS << AV8L_FAST_TCR_SH0_SHIFT) |

		      (AV8L_FAST_TCR_RGN_NC << AV8L_FAST_TCR_IRGN0_SHIFT) |

		      (AV8L_FAST_TCR_RGN_NC << AV8L_FAST_TCR_ORGN0_SHIFT);

drivers/iommu/io-pgtable.h

+5 −0
Original line number Diff line number Diff line
@@ -74,11 +74,16 @@ struct io_pgtable_cfg { 
	 *	PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit

	 *	when the SoC is in "4GB mode" and they can only access the high

	 *	remap of DRAM (0x1_00000000 to 0x1_ffffffff).

	 *

	 * IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT: Override the attributes

	 *	set in TCR for the page table walker. Use attributes specified

	 *	by the upstream hw instead.

	 */

	#define IO_PGTABLE_QUIRK_ARM_NS		BIT(0)

	#define IO_PGTABLE_QUIRK_NO_PERMS	BIT(1)

	#define IO_PGTABLE_QUIRK_TLBI_ON_MAP	BIT(2)

	#define IO_PGTABLE_QUIRK_ARM_MTK_4GB	BIT(3)

	#define IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT	BIT(4)

	unsigned long			quirks;

	unsigned long			pgsize_bitmap;

	unsigned int			ias;