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Commit ce2f50b4 authored by Naveen Gupta's avatar Naveen Gupta Committed by Wim Van Sebroeck
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[WATCHDOG] i6300esb-set_correct_reload_register_bit



This patch writes into bit 8 of the reload register to perform the
correct 'Reload Sequence' instead of writing into bit 4 of Watchdog for
Intel 6300ESB chipset.

Signed-off-by: default avatarNaveen Gupta <ngupta@google.com>
Signed-off-by: default avatarDavid Hardeman <david@2gen.com>
Signed-off-by: default avatarWim Van Sebroeck <wim@iguana.be>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
parent 28562af3
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+3 −3
Original line number Original line Diff line number Diff line
@@ -109,7 +109,7 @@ static int esb_timer_stop(void)
	spin_lock(&esb_lock);
	spin_lock(&esb_lock);
	/* First, reset timers as suggested by the docs */
	/* First, reset timers as suggested by the docs */
	esb_unlock_registers();
	esb_unlock_registers();
	writew(0x10, ESB_RELOAD_REG);
	writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
	/* Then disable the WDT */
	/* Then disable the WDT */
	pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x0);
	pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x0);
	pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val);
	pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val);
@@ -123,7 +123,7 @@ static void esb_timer_keepalive(void)
{
{
	spin_lock(&esb_lock);
	spin_lock(&esb_lock);
	esb_unlock_registers();
	esb_unlock_registers();
	writew(0x10, ESB_RELOAD_REG);
	writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
        /* FIXME: Do we need to flush anything here? */
        /* FIXME: Do we need to flush anything here? */
	spin_unlock(&esb_lock);
	spin_unlock(&esb_lock);
}
}
@@ -153,7 +153,7 @@ static int esb_timer_set_heartbeat(int time)


        /* Reload */
        /* Reload */
	esb_unlock_registers();
	esb_unlock_registers();
	writew(0x10, ESB_RELOAD_REG);
	writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);


	/* FIXME: Do we need to flush everything out? */
	/* FIXME: Do we need to flush everything out? */


+2 −0
Original line number Original line Diff line number Diff line
@@ -54,6 +54,8 @@
#define ESB_WDT_FREQ    ( 0x01 << 2 )   /* Decrement frequency               */
#define ESB_WDT_FREQ    ( 0x01 << 2 )   /* Decrement frequency               */
#define ESB_WDT_INTTYPE ( 0x11 << 0 )   /* Interrupt type on timer1 timeout  */
#define ESB_WDT_INTTYPE ( 0x11 << 0 )   /* Interrupt type on timer1 timeout  */


/* Reload register bits */
#define ESB_WDT_RELOAD ( 0x01 << 8 )    /* prevent timeout                   */


/*
/*
 * Some magic constants
 * Some magic constants