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Commit ccfda00e authored by Satyajit Desai's avatar Satyajit Desai Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add support for TMC ETR streaming on SDM845 



Add byte counter interrupt support to the TMC ETR device.
Move CSR device in order for it to probe before TMC ETR.

Change-Id: I294f0c8edd182eed57b7db6c1b47f23ac6fc4fa7
Signed-off-by: default avatarSatyajit Desai <sadesai@codeaurora.org>
parent 3897887e

arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi

+13 −10
Original line number Diff line number Diff line
@@ -12,6 +12,16 @@ 


&soc {



	csr: csr@6001000 {

		compatible = "qcom,coresight-csr";

		reg = <0x6001000 0x1000>;

		reg-names = "csr-base";



		coresight-name = "coresight-csr";



		qcom,blk-size = <1>;

	};



	replicator_qdss: replicator@6046000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b909>;
@@ -271,6 +281,9 @@ 
		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";



		interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>;

		interrupt-names = "byte-cntr-irq";



		port {

			tmc_etr_in_replicator: endpoint {

				slave-mode;
@@ -397,16 +410,6 @@ 
		clock-names = "apb_pclk";

	};



	csr: csr@6001000 {

		compatible = "qcom,coresight-csr";

		reg = <0x6001000 0x1000>;

		reg-names = "csr-base";



		coresight-name = "coresight-csr";



		qcom,blk-size = <1>;

	};



	funnel_in0: funnel@0x6041000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b908>;