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Commit cc8006e2 authored by Jigarkumar Zala's avatar Jigarkumar Zala
Browse files

msm: camera: cci: Correct base address to calculate right offset 



Base address is not correct in dump register function. After update
correct base address dump register function can calculate correct
offset for CCI registers for debugging. Also, Update debug log
level when irq error is triggered.

Change-Id: I1a01f44967678d3170b211362a7c6770168128ef
Signed-off-by: default avatarJigarkumar Zala <jzala@codeaurora.org>
parent d1a9fffc

drivers/media/platform/msm/camera/cam_sensor_module/cam_cci/cam_cci_core.c

+14 −13
Original line number Diff line number Diff line 
/* Copyright (c) 2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -183,45 +183,46 @@ static void cam_cci_dump_registers(struct cci_device *cci_dev, 
	uint32_t read_val = 0;

	uint32_t i = 0;

	uint32_t reg_offset = 0;

	void __iomem *base = cci_dev->soc_info.reg_map[0].mem_base;



	/* CCI Top Registers */

	CAM_DBG(CAM_CCI, "****CCI TOP Registers ****");

	CAM_INFO(CAM_CCI, "****CCI TOP Registers ****");

	for (i = 0; i < DEBUG_TOP_REG_COUNT; i++) {

		reg_offset = DEBUG_TOP_REG_START + i * 4;

		read_val = cam_io_r_mb(cci_dev->base + reg_offset);

		CAM_DBG(CAM_CCI, "offset = 0x%X value = 0x%X",

		read_val = cam_io_r_mb(base + reg_offset);

		CAM_INFO(CAM_CCI, "offset = 0x%X value = 0x%X",

			reg_offset, read_val);

	}



	/* CCI Master registers */

	CAM_DBG(CAM_CCI, "****CCI MASTER %d Registers ****",

	CAM_INFO(CAM_CCI, "****CCI MASTER %d Registers ****",

		master);

	for (i = 0; i < DEBUG_MASTER_REG_COUNT; i++) {

		if (i == 6)

			continue;

		reg_offset = DEBUG_MASTER_REG_START + master*0x100 + i * 4;

		read_val = cam_io_r_mb(cci_dev->base + reg_offset);

		CAM_DBG(CAM_CCI, "offset = 0x%X value = 0x%X",

		read_val = cam_io_r_mb(base + reg_offset);

		CAM_INFO(CAM_CCI, "offset = 0x%X value = 0x%X",

			reg_offset, read_val);

	}



	/* CCI Master Queue registers */

	CAM_DBG(CAM_CCI, " **** CCI MASTER%d QUEUE%d Registers ****",

	CAM_INFO(CAM_CCI, " **** CCI MASTER%d QUEUE%d Registers ****",

		master, queue);

	for (i = 0; i < DEBUG_MASTER_QUEUE_REG_COUNT; i++) {

		reg_offset = DEBUG_MASTER_QUEUE_REG_START +  master*0x200 +

			queue*0x100 + i * 4;

		read_val = cam_io_r_mb(cci_dev->base + reg_offset);

		CAM_DBG(CAM_CCI, "offset = 0x%X value = 0x%X",

		read_val = cam_io_r_mb(base + reg_offset);

		CAM_INFO(CAM_CCI, "offset = 0x%X value = 0x%X",

			reg_offset, read_val);

	}



	/* CCI Interrupt registers */

	CAM_DBG(CAM_CCI, " ****CCI Interrupt Registers ****");

	CAM_INFO(CAM_CCI, " ****CCI Interrupt Registers ****");

	for (i = 0; i < DEBUG_INTR_REG_COUNT; i++) {

		reg_offset = DEBUG_INTR_REG_START + i * 4;

		read_val = cam_io_r_mb(cci_dev->base + reg_offset);

		CAM_DBG(CAM_CCI, "offset = 0x%X value = 0x%X",

		read_val = cam_io_r_mb(base + reg_offset);

		CAM_INFO(CAM_CCI, "offset = 0x%X value = 0x%X",

			reg_offset, read_val);

	}

}