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Commit cc4d9e15 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/sde: add null checks for pingpong and encoder hardware"

parents 5cd0f4e0 6a5359d8

drivers/gpu/drm/msm/sde/sde_encoder.c

+13 −3
Original line number Diff line number Diff line
@@ -637,7 +637,7 @@ void sde_encoder_helper_split_config( 


		if (hw_mdptop->ops.setup_split_pipe)

			hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);

	} else {

	} else if (sde_enc->hw_pp[0]) {

		/*

		 * slave encoder

		 * - determine split index from master index,
@@ -2277,6 +2277,11 @@ static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc, 
		return;

	}



	if (!phys->hw_pp) {

		SDE_ERROR("invalid pingpong hw\n");

		return;

	}



	ctl = phys->hw_ctl;

	if (!ctl || !ctl->ops.trigger_flush) {

		SDE_ERROR("missing trigger cb\n");
@@ -2318,7 +2323,12 @@ static inline void _sde_encoder_trigger_start(struct sde_encoder_phys *phys) 
	struct sde_hw_ctl *ctl;



	if (!phys) {

		SDE_ERROR("invalid encoder\n");

		SDE_ERROR("invalid argument(s)\n");

		return;

	}



	if (!phys->hw_pp) {

		SDE_ERROR("invalid pingpong hw\n");

		return;

	}
@@ -2580,7 +2590,7 @@ static void _sde_encoder_update_master(struct drm_encoder *drm_enc, 
		bool active;



		phys = sde_enc->phys_encs[i];

		if (!phys || !phys->ops.update_split_role)

		if (!phys || !phys->ops.update_split_role || !phys->hw_pp)

			continue;



		active = test_bit(i, &params->affected_displays);

drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c

+13 −4
Original line number Diff line number Diff line
@@ -131,6 +131,9 @@ static void _sde_encoder_phys_cmd_update_flush_mask( 
	struct sde_hw_ctl *ctl;

	u32 flush_mask = 0;



	if (!phys_enc)

		return;



	ctl = phys_enc->hw_ctl;

	if (!ctl || !ctl->ops.get_bitmask_intf ||

			!ctl->ops.update_pending_flush)
@@ -151,6 +154,9 @@ static void _sde_encoder_phys_cmd_update_intf_cfg( 
	struct sde_hw_ctl *ctl;

	struct sde_hw_intf_cfg intf_cfg = { 0 };



	if (!phys_enc)

		return;



	ctl = phys_enc->hw_ctl;

	if (!ctl || !ctl->ops.setup_intf_cfg)

		return;
@@ -410,6 +416,9 @@ static int _sde_encoder_phys_cmd_handle_ppdone_timeout( 
				| SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE;

	bool do_log = false;



	if (!phys_enc || !phys_enc->hw_pp || !phys_enc->hw_ctl)

		return -EINVAL;



	cmd_enc->pp_timeout_report_cnt++;

	if (cmd_enc->pp_timeout_report_cnt == PP_TIMEOUT_MAX_TRIALS) {

		frame_event |= SDE_ENCODER_FRAME_EVENT_PANEL_DEAD;
@@ -603,7 +612,7 @@ static int sde_encoder_phys_cmd_control_vblank_irq( 
	int ret = 0;

	int refcount;



	if (!phys_enc) {

	if (!phys_enc || !phys_enc->hw_pp) {

		SDE_ERROR("invalid encoder\n");

		return -EINVAL;

	}
@@ -695,7 +704,7 @@ static void sde_encoder_phys_cmd_tearcheck_config( 
	struct msm_drm_private *priv;

	struct sde_kms *sde_kms;



	if (!phys_enc) {

	if (!phys_enc || !phys_enc->hw_pp) {

		SDE_ERROR("invalid encoder\n");

		return;

	}
@@ -991,8 +1000,8 @@ static int _sde_encoder_phys_cmd_wait_for_ctl_start( 
	struct sde_encoder_wait_info wait_info;

	int ret;



	if (!phys_enc) {

		SDE_ERROR("invalid encoder\n");

	if (!phys_enc || !phys_enc->hw_ctl) {

		SDE_ERROR("invalid argument(s)\n");

		return -EINVAL;

	}

drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c

+3 −0
Original line number Diff line number Diff line
@@ -385,6 +385,9 @@ static void sde_encoder_phys_vid_vblank_irq(void *arg, int irq_idx) 
		return;



	hw_ctl = phys_enc->hw_ctl;

	if (!hw_ctl)

		return;



	SDE_ATRACE_BEGIN("vblank_irq");



	/* signal only for master, where there is a pending kickoff */

drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c

+23 −5
Original line number Diff line number Diff line
@@ -156,10 +156,18 @@ void sde_encoder_phys_setup_cdm(struct sde_encoder_phys *phys_enc, 
		struct drm_framebuffer *fb, const struct sde_format *format,

		struct sde_rect *wb_roi)

{

	struct sde_hw_cdm *hw_cdm = phys_enc->hw_cdm;

	struct sde_hw_cdm_cfg *cdm_cfg = &phys_enc->cdm_cfg;

	struct sde_hw_cdm *hw_cdm;

	struct sde_hw_cdm_cfg *cdm_cfg;

	int ret;



	if (!phys_enc || !format)

		return;



	cdm_cfg = &phys_enc->cdm_cfg;

	hw_cdm = phys_enc->hw_cdm;

	if (!hw_cdm)

		return;



	if (!SDE_FORMAT_IS_YUV(format)) {

		SDE_DEBUG("[cdm_disable fmt:%x]\n",

				format->base.pixel_format);
@@ -172,6 +180,9 @@ void sde_encoder_phys_setup_cdm(struct sde_encoder_phys *phys_enc, 


	memset(cdm_cfg, 0, sizeof(struct sde_hw_cdm_cfg));



	if (!wb_roi)

		return;



	cdm_cfg->output_width = wb_roi->w;

	cdm_cfg->output_height = wb_roi->h;

	cdm_cfg->output_fmt = format;
@@ -512,11 +523,18 @@ static int sde_encoder_phys_wb_atomic_check( 
static void _sde_encoder_phys_wb_update_flush(struct sde_encoder_phys *phys_enc)

{

	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);

	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;

	struct sde_hw_ctl *hw_ctl = phys_enc->hw_ctl;

	struct sde_hw_cdm *hw_cdm = phys_enc->hw_cdm;

	struct sde_hw_wb *hw_wb;

	struct sde_hw_ctl *hw_ctl;

	struct sde_hw_cdm *hw_cdm;

	u32 flush_mask = 0;



	if (!phys_enc)

		return;



	hw_wb = wb_enc->hw_wb;

	hw_ctl = phys_enc->hw_ctl;

	hw_cdm = phys_enc->hw_cdm;



	SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);



	if (!hw_ctl) {

drivers/gpu/drm/msm/sde/sde_hw_pingpong.c

+32 −8
Original line number Diff line number Diff line
@@ -69,9 +69,13 @@ static struct sde_pingpong_cfg *_pingpong_offset(enum sde_pingpong pp, 
static int sde_hw_pp_setup_te_config(struct sde_hw_pingpong *pp,

		struct sde_hw_tear_check *te)

{

	struct sde_hw_blk_reg_map *c = &pp->hw;

	struct sde_hw_blk_reg_map *c;

	int cfg;



	if (!pp || !te)

		return -EINVAL;

	c = &pp->hw;



	cfg = BIT(19); /*VSYNC_COUNTER_EN */

	if (te->hw_vsync_mode)

		cfg |= BIT(20);
@@ -149,26 +153,38 @@ static int sde_hw_pp_poll_timeout_wr_ptr(struct sde_hw_pingpong *pp, 


static void sde_hw_pp_dsc_enable(struct sde_hw_pingpong *pp)

{

	struct sde_hw_blk_reg_map *c = &pp->hw;

	struct sde_hw_blk_reg_map *c;



	if (!pp)

		return;

	c = &pp->hw;



	SDE_REG_WRITE(c, PP_DSC_MODE, 1);

}



static void sde_hw_pp_dsc_disable(struct sde_hw_pingpong *pp)

{

	struct sde_hw_blk_reg_map *c = &pp->hw;

	struct sde_hw_blk_reg_map *c;



	if (!pp)

		return;

	c = &pp->hw;



	SDE_REG_WRITE(c, PP_DSC_MODE, 0);

}



static int sde_hw_pp_setup_dsc(struct sde_hw_pingpong *pp)

{

	struct sde_hw_blk_reg_map *pp_c = &pp->hw;

	struct sde_hw_blk_reg_map *c;

	int data;



	data = SDE_REG_READ(pp_c, PP_DCE_DATA_OUT_SWAP);

	if (!pp)

		return -EINVAL;

	c = &pp->hw;



	data = SDE_REG_READ(c, PP_DCE_DATA_OUT_SWAP);

	data |= BIT(18); /* endian flip */

	SDE_REG_WRITE(pp_c, PP_DCE_DATA_OUT_SWAP, data);

	SDE_REG_WRITE(c, PP_DCE_DATA_OUT_SWAP, data);

	return 0;

}
@@ -225,7 +241,11 @@ static int sde_hw_pp_setup_dither_v1(struct sde_hw_pingpong *pp, 


static int sde_hw_pp_enable_te(struct sde_hw_pingpong *pp, bool enable)

{

	struct sde_hw_blk_reg_map *c = &pp->hw;

	struct sde_hw_blk_reg_map *c;



	if (!pp)

		return -EINVAL;

	c = &pp->hw;



	SDE_REG_WRITE(c, PP_TEAR_CHECK_EN, enable);

	return 0;
@@ -257,9 +277,13 @@ static int sde_hw_pp_connect_external_te(struct sde_hw_pingpong *pp, 
static int sde_hw_pp_get_vsync_info(struct sde_hw_pingpong *pp,

		struct sde_hw_pp_vsync_info *info)

{

	struct sde_hw_blk_reg_map *c = &pp->hw;

	struct sde_hw_blk_reg_map *c;

	u32 val;



	if (!pp || !info)

		return -EINVAL;

	c = &pp->hw;



	val = SDE_REG_READ(c, PP_VSYNC_INIT_VAL);

	info->rd_ptr_init_val = val & 0xffff;