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Commit cbdf19be authored by Shrenuj Bansal's avatar Shrenuj Bansal
Browse files

msm: kgsl: Correct the register base address used for HLSQ/SP/TP snapshot 



Fix the base addresses used to calculate register offsets relative
to the aperture in the snapshot for HLSQ/SP/TP through the HLSQ
debug bus.

Change-Id: Ia73e6ef9d28930d99033fef5a41f91588837ecd6
Signed-off-by: default avatarShrenuj Bansal <shrenujb@codeaurora.org>
parent 417dbabb

drivers/gpu/msm/adreno_a6xx_snapshot.c

+12 −12
Original line number Diff line number Diff line
@@ -126,31 +126,31 @@ static struct a6xx_cluster_dbgahb_registers { 
		ARRAY_SIZE(a6xx_sp_vs_hlsq_cluster) / 2 },

	{ CP_CLUSTER_SP_VS, 0x0002A000, 0x21, a6xx_sp_vs_sp_cluster,

		ARRAY_SIZE(a6xx_sp_vs_sp_cluster) / 2 },

	{ CP_CLUSTER_SP_VS, 0x0002EC00, 0x41, a6xx_hlsq_duplicate_cluster,

	{ CP_CLUSTER_SP_VS, 0x0002E000, 0x41, a6xx_hlsq_duplicate_cluster,

		ARRAY_SIZE(a6xx_hlsq_duplicate_cluster) / 2 },

	{ CP_CLUSTER_SP_VS, 0x0002F000, 0x45, a6xx_hlsq_2d_duplicate_cluster,

		ARRAY_SIZE(a6xx_hlsq_2d_duplicate_cluster) / 2 },

	{ CP_CLUSTER_SP_VS, 0x0002AC00, 0x21, a6xx_sp_duplicate_cluster,

	{ CP_CLUSTER_SP_VS, 0x0002A000, 0x21, a6xx_sp_duplicate_cluster,

		ARRAY_SIZE(a6xx_sp_duplicate_cluster) / 2 },

	{ CP_CLUSTER_SP_VS, 0x0002CC00, 0x1, a6xx_tp_duplicate_cluster,

	{ CP_CLUSTER_SP_VS, 0x0002C000, 0x1, a6xx_tp_duplicate_cluster,

		ARRAY_SIZE(a6xx_tp_duplicate_cluster) / 2 },

	{ CP_CLUSTER_SP_PS, 0x0002E600, 0x42, a6xx_sp_ps_hlsq_cluster,

	{ CP_CLUSTER_SP_PS, 0x0002E000, 0x42, a6xx_sp_ps_hlsq_cluster,

		ARRAY_SIZE(a6xx_sp_ps_hlsq_cluster) / 2 },

	{ CP_CLUSTER_SP_PS, 0x0002F300, 0x46, a6xx_sp_ps_hlsq_2d_cluster,

	{ CP_CLUSTER_SP_PS, 0x0002F000, 0x46, a6xx_sp_ps_hlsq_2d_cluster,

		ARRAY_SIZE(a6xx_sp_ps_hlsq_2d_cluster) / 2 },

	{ CP_CLUSTER_SP_PS, 0x0002A600, 0x22, a6xx_sp_ps_sp_cluster,

	{ CP_CLUSTER_SP_PS, 0x0002A000, 0x22, a6xx_sp_ps_sp_cluster,

		ARRAY_SIZE(a6xx_sp_ps_sp_cluster) / 2 },

	{ CP_CLUSTER_SP_PS, 0x0002B300, 0x26, a6xx_sp_ps_sp_2d_cluster,

	{ CP_CLUSTER_SP_PS, 0x0002B000, 0x26, a6xx_sp_ps_sp_2d_cluster,

		ARRAY_SIZE(a6xx_sp_ps_sp_2d_cluster) / 2 },

	{ CP_CLUSTER_SP_PS, 0x0002C600, 0x2, a6xx_sp_ps_tp_cluster,

	{ CP_CLUSTER_SP_PS, 0x0002C000, 0x2, a6xx_sp_ps_tp_cluster,

		ARRAY_SIZE(a6xx_sp_ps_tp_cluster) / 2 },

	{ CP_CLUSTER_SP_PS, 0x0002D300, 0x6, a6xx_sp_ps_tp_2d_cluster,

	{ CP_CLUSTER_SP_PS, 0x0002D000, 0x6, a6xx_sp_ps_tp_2d_cluster,

		ARRAY_SIZE(a6xx_sp_ps_tp_2d_cluster) / 2 },

	{ CP_CLUSTER_SP_PS, 0x0002EC00, 0x42, a6xx_hlsq_duplicate_cluster,

	{ CP_CLUSTER_SP_PS, 0x0002E000, 0x42, a6xx_hlsq_duplicate_cluster,

		ARRAY_SIZE(a6xx_hlsq_duplicate_cluster) / 2 },

	{ CP_CLUSTER_SP_VS, 0x0002AC00, 0x22, a6xx_sp_duplicate_cluster,

	{ CP_CLUSTER_SP_VS, 0x0002A000, 0x22, a6xx_sp_duplicate_cluster,

		ARRAY_SIZE(a6xx_sp_duplicate_cluster) / 2 },

	{ CP_CLUSTER_SP_VS, 0x0002CC00, 0x2, a6xx_tp_duplicate_cluster,

	{ CP_CLUSTER_SP_VS, 0x0002C000, 0x2, a6xx_tp_duplicate_cluster,

		ARRAY_SIZE(a6xx_tp_duplicate_cluster) / 2 },

};