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Commit cb418b34 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

Merge branch 'ralf-3.7' of... 

Merge branch 'ralf-3.7' of git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
parents 77a0d763 ff401e52

arch/mips/Kbuild.platforms

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ platforms += lasat 
platforms += loongson

platforms += loongson1

platforms += mti-malta

platforms += mti-sead3

platforms += netlogic

platforms += pmc-sierra

platforms += pnx833x

arch/mips/Kconfig

+30 −2
Original line number Diff line number Diff line
@@ -322,6 +322,36 @@ config MIPS_MALTA 
	  This enables support for the MIPS Technologies Malta evaluation

	  board.



config MIPS_SEAD3

	bool "MIPS SEAD3 board"

	select BOOT_ELF32

	select BOOT_RAW

	select CEVT_R4K

	select CSRC_R4K

	select CPU_MIPSR2_IRQ_VI

	select CPU_MIPSR2_IRQ_EI

	select DMA_NONCOHERENT

	select IRQ_CPU

	select IRQ_GIC

	select MIPS_BOARDS_GEN

	select MIPS_CPU_SCACHE

	select MIPS_MSC

	select SYS_HAS_CPU_MIPS32_R1

	select SYS_HAS_CPU_MIPS32_R2

	select SYS_HAS_CPU_MIPS64_R1

	select SYS_HAS_EARLY_PRINTK

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_SUPPORTS_SMARTMIPS

	select USB_ARCH_HAS_EHCI

	select USB_EHCI_BIG_ENDIAN_DESC

	select USB_EHCI_BIG_ENDIAN_MMIO

	help

	  This enables support for the MIPS Technologies SEAD3 evaluation

	  board.



config NEC_MARKEINS

	bool "NEC EMMA2RH Mark-eins board"

	select SOC_EMMA2RH
@@ -1732,7 +1762,6 @@ config HARDWARE_WATCHPOINTS 
menu "Kernel type"



choice



	prompt "Kernel code model"

	help

	  You should only select this option if you have a workload that
@@ -1938,7 +1967,6 @@ config SCHED_SMT 
config SYS_SUPPORTS_SCHED_SMT

	bool





config SYS_SUPPORTS_MULTITHREADING

	bool

arch/mips/configs/sead3_defconfig

0 → 100644
+124 −0
Original line number Diff line number Diff line 
CONFIG_MIPS_SEAD3=y

CONFIG_CPU_LITTLE_ENDIAN=y

CONFIG_CPU_MIPS32_R2=y

CONFIG_HZ_100=y

CONFIG_EXPERIMENTAL=y

CONFIG_SYSVIPC=y

CONFIG_POSIX_MQUEUE=y

CONFIG_NO_HZ=y

CONFIG_HIGH_RES_TIMERS=y

CONFIG_IKCONFIG=y

CONFIG_IKCONFIG_PROC=y

CONFIG_LOG_BUF_SHIFT=15

CONFIG_EMBEDDED=y

CONFIG_SLAB=y

CONFIG_PROFILING=y

CONFIG_OPROFILE=y

CONFIG_MODULES=y

# CONFIG_BLK_DEV_BSG is not set

# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set

CONFIG_NET=y

CONFIG_PACKET=y

CONFIG_UNIX=y

CONFIG_INET=y

CONFIG_IP_PNP=y

CONFIG_IP_PNP_DHCP=y

CONFIG_IP_PNP_BOOTP=y

# CONFIG_INET_XFRM_MODE_TRANSPORT is not set

# CONFIG_INET_XFRM_MODE_TUNNEL is not set

# CONFIG_INET_XFRM_MODE_BEET is not set

# CONFIG_INET_LRO is not set

# CONFIG_INET_DIAG is not set

# CONFIG_IPV6 is not set

# CONFIG_WIRELESS is not set

CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"

CONFIG_MTD=y

CONFIG_MTD_CHAR=y

CONFIG_MTD_BLOCK=y

CONFIG_MTD_CFI=y

CONFIG_MTD_CFI_INTELEXT=y

CONFIG_MTD_PHYSMAP=y

CONFIG_MTD_UBI=y

CONFIG_MTD_UBI_GLUEBI=y

CONFIG_BLK_DEV_LOOP=y

CONFIG_BLK_DEV_CRYPTOLOOP=m

CONFIG_SCSI=y

# CONFIG_SCSI_PROC_FS is not set

CONFIG_BLK_DEV_SD=y

CONFIG_CHR_DEV_SG=y

# CONFIG_SCSI_LOWLEVEL is not set

CONFIG_NETDEVICES=y

CONFIG_SMSC911X=y

# CONFIG_NET_VENDOR_WIZNET is not set

CONFIG_MARVELL_PHY=y

CONFIG_DAVICOM_PHY=y

CONFIG_QSEMI_PHY=y

CONFIG_LXT_PHY=y

CONFIG_CICADA_PHY=y

CONFIG_VITESSE_PHY=y

CONFIG_SMSC_PHY=y

CONFIG_BROADCOM_PHY=y

CONFIG_ICPLUS_PHY=y

# CONFIG_WLAN is not set

# CONFIG_INPUT_MOUSEDEV is not set

# CONFIG_INPUT_KEYBOARD is not set

# CONFIG_INPUT_MOUSE is not set

# CONFIG_SERIO is not set

# CONFIG_CONSOLE_TRANSLATIONS is not set

CONFIG_VT_HW_CONSOLE_BINDING=y

CONFIG_LEGACY_PTY_COUNT=32

CONFIG_SERIAL_8250=y

CONFIG_SERIAL_8250_CONSOLE=y

CONFIG_SERIAL_8250_NR_UARTS=2

CONFIG_SERIAL_8250_RUNTIME_UARTS=2

# CONFIG_HW_RANDOM is not set

CONFIG_I2C=y

# CONFIG_I2C_COMPAT is not set

CONFIG_I2C_CHARDEV=y

# CONFIG_I2C_HELPER_AUTO is not set

CONFIG_SPI=y

CONFIG_SENSORS_ADT7475=y

CONFIG_BACKLIGHT_LCD_SUPPORT=y

CONFIG_LCD_CLASS_DEVICE=y

CONFIG_BACKLIGHT_CLASS_DEVICE=y

# CONFIG_VGA_CONSOLE is not set

CONFIG_USB=y

CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

CONFIG_USB_EHCI_HCD=y

CONFIG_USB_EHCI_ROOT_HUB_TT=y

CONFIG_USB_STORAGE=y

CONFIG_MMC=y

CONFIG_MMC_DEBUG=y

CONFIG_MMC_SPI=y

CONFIG_NEW_LEDS=y

CONFIG_LEDS_CLASS=y

CONFIG_LEDS_TRIGGERS=y

CONFIG_LEDS_TRIGGER_HEARTBEAT=y

CONFIG_RTC_CLASS=y

CONFIG_RTC_DRV_M41T80=y

CONFIG_EXT3_FS=y

# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set

CONFIG_XFS_FS=y

CONFIG_XFS_QUOTA=y

CONFIG_XFS_POSIX_ACL=y

CONFIG_QUOTA=y

# CONFIG_PRINT_QUOTA_WARNING is not set

CONFIG_MSDOS_FS=m

CONFIG_VFAT_FS=m

CONFIG_TMPFS=y

CONFIG_JFFS2_FS=y

CONFIG_NFS_FS=y

CONFIG_ROOT_NFS=y

CONFIG_NLS_CODEPAGE_437=y

CONFIG_NLS_ASCII=y

CONFIG_NLS_ISO8859_1=y

CONFIG_NLS_ISO8859_15=y

CONFIG_NLS_UTF8=y

# CONFIG_FTRACE is not set

CONFIG_CRYPTO=y

CONFIG_CRYPTO_CBC=y

CONFIG_CRYPTO_ECB=y

CONFIG_CRYPTO_AES=y

CONFIG_CRYPTO_ARC4=y

# CONFIG_CRYPTO_ANSI_CPRNG is not set

# CONFIG_CRYPTO_HW is not set

arch/mips/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -94,6 +94,7 @@ 
#define PRID_IMP_24KE		0x9600

#define PRID_IMP_74K		0x9700

#define PRID_IMP_1004K		0x9900

#define PRID_IMP_1074K		0x9a00

#define PRID_IMP_M14KC		0x9c00



/*

arch/mips/include/asm/gic.h

+39 −10
Original line number Diff line number Diff line
@@ -38,8 +38,8 @@ 
	(_gic_base + segment##_##SECTION_OFS + offset)



#ifdef GICISBYTELITTLEENDIAN

#define GICREAD(reg, data)	(data) = (reg), (data) = le32_to_cpu(data)

#define GICWRITE(reg, data)	(reg) = cpu_to_le32(data)

#define GICREAD(reg, data)	((data) = (reg), (data) = le32_to_cpu(data))

#define GICWRITE(reg, data)	((reg) = cpu_to_le32(data))

#define GICBIS(reg, bits)			\

	({unsigned int data;			\

		GICREAD(reg, data);		\
@@ -48,9 +48,9 @@ 
	})



#else

#define GICREAD(reg, data)	(data) = (reg)

#define GICWRITE(reg, data)	(reg) = (data)

#define GICBIS(reg, bits)	(reg) |= (bits)

#define GICREAD(reg, data)	((data) = (reg))

#define GICWRITE(reg, data)	((reg) = (data))

#define GICBIS(reg, bits)	((reg) |= (bits))

#endif
@@ -341,15 +341,44 @@ struct gic_shared_intr_map { 
	unsigned int local_intr_mask;

};



/* GIC nomenclature for Core Interrupt Pins. */

#define GIC_CPU_INT0		0 /* Core Interrupt 2 */

#define GIC_CPU_INT1		1 /* .                */

#define GIC_CPU_INT2		2 /* .                */

#define GIC_CPU_INT3		3 /* .                */

#define GIC_CPU_INT4		4 /* .                */

#define GIC_CPU_INT5		5 /* Core Interrupt 5 */



/* Local GIC interrupts. */

#define GIC_INT_TMR		(GIC_CPU_INT5)

#define GIC_INT_PERFCTR		(GIC_CPU_INT5)



/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */

#define GIC_CPU_TO_VEC_OFFSET	(2)



/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */

#define GIC_PIN_TO_VEC_OFFSET	(1)



extern unsigned long _gic_base;

extern unsigned int gic_irq_base;

extern unsigned int gic_irq_flags[];

extern struct gic_shared_intr_map gic_shared_intr_map[];



extern void gic_init(unsigned long gic_base_addr,

	unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,

	unsigned int intrmap_size, unsigned int irqbase);



extern void gic_clocksource_init(unsigned int);

extern unsigned int gic_get_int(void);

extern void gic_send_ipi(unsigned int intr);

extern unsigned int plat_ipi_call_int_xlate(unsigned int);

extern unsigned int plat_ipi_resched_int_xlate(unsigned int);

extern void gic_bind_eic_interrupt(int irq, int set);

extern unsigned int gic_get_timer_pending(void);

extern void gic_enable_interrupt(int irq_vec);

extern void gic_disable_interrupt(int irq_vec);

extern void gic_irq_ack(struct irq_data *d);

extern void gic_finish_irq(struct irq_data *d);

extern void gic_platform_init(int irqs, struct irq_chip *irq_controller);



#endif /* _ASM_GICREGS_H */