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Commit cb1e06e0 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nvf0/gr: initial register/context setup 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 507cd5b5

drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c

+226 −34
Original line number Diff line number Diff line
@@ -2190,6 +2190,15 @@ nve0_grctx_generate_902d(struct nvc0_graph_priv *priv) 
static void

nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv)

{

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x404004, 0x00000000);

		nv_wr32(priv, 0x404008, 0x00000000);

		nv_wr32(priv, 0x40400c, 0x00000000);

		break;

	default:

		break;

	}

	nv_wr32(priv, 0x404010, 0x0);

	nv_wr32(priv, 0x404014, 0x0);

	nv_wr32(priv, 0x404018, 0x0);
@@ -2197,6 +2206,19 @@ nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv) 
	nv_wr32(priv, 0x404020, 0x0);

	nv_wr32(priv, 0x404024, 0xe000);

	nv_wr32(priv, 0x404028, 0x0);

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x40402c, 0x00000000);

		nv_wr32(priv, 0x404030, 0x00000000);

		nv_wr32(priv, 0x404034, 0x00000000);

		nv_wr32(priv, 0x404038, 0x00000000);

		nv_wr32(priv, 0x40403c, 0x00000000);

		nv_wr32(priv, 0x404040, 0x00000000);

		nv_wr32(priv, 0x404044, 0x00000000);

		break;

	default:

		break;

	}

	nv_wr32(priv, 0x4040a8, 0x0);

	nv_wr32(priv, 0x4040ac, 0x0);

	nv_wr32(priv, 0x4040b0, 0x0);
@@ -2214,6 +2236,22 @@ nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv) 
	nv_wr32(priv, 0x4040e4, 0x0);

	nv_wr32(priv, 0x4040e8, 0x1000);

	nv_wr32(priv, 0x4040f8, 0x0);

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x404100, 0x00000000);

		nv_wr32(priv, 0x404104, 0x00000000);

		nv_wr32(priv, 0x404108, 0x00000000);

		nv_wr32(priv, 0x40410c, 0x00000000);

		nv_wr32(priv, 0x404110, 0x00000000);

		nv_wr32(priv, 0x404114, 0x00000000);

		nv_wr32(priv, 0x404118, 0x00000000);

		nv_wr32(priv, 0x40411c, 0x00000000);

		nv_wr32(priv, 0x404120, 0x00000000);

		nv_wr32(priv, 0x404124, 0x00000000);

		break;

	default:

		break;

	}

	nv_wr32(priv, 0x404130, 0x0);

	nv_wr32(priv, 0x404134, 0x0);

	nv_wr32(priv, 0x404138, 0x20000040);
@@ -2221,14 +2259,32 @@ nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv) 
	nv_wr32(priv, 0x404154, 0x400);

	nv_wr32(priv, 0x404158, 0x200);

	nv_wr32(priv, 0x404164, 0x55);

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x40417c, 0x00000000);

		nv_wr32(priv, 0x404180, 0x00000000);

		break;

	default:

		break;

	}

	nv_wr32(priv, 0x4041a0, 0x0);

	nv_wr32(priv, 0x4041a4, 0x0);

	nv_wr32(priv, 0x4041a8, 0x0);

	nv_wr32(priv, 0x4041ac, 0x0);

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x404200, 0xa197);

		nv_wr32(priv, 0x404204, 0xa1c0);

		nv_wr32(priv, 0x404208, 0xa140);

		nv_wr32(priv, 0x40420c, 0x902d);

		break;

	default:

		nv_wr32(priv, 0x404200, 0x0);

		nv_wr32(priv, 0x404204, 0x0);

		nv_wr32(priv, 0x404208, 0x0);

		nv_wr32(priv, 0x40420c, 0x0);

		break;

	}

}



static void
@@ -2246,7 +2302,13 @@ nve0_graph_generate_unk44xx(struct nvc0_graph_priv *priv) 
	nv_wr32(priv, 0x404428, 0x0);

	nv_wr32(priv, 0x40442c, 0x0);

	nv_wr32(priv, 0x404430, 0x0);

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		break;

	default:

		nv_wr32(priv, 0x404434, 0x0);

		break;

	}

	nv_wr32(priv, 0x404438, 0x0);

	nv_wr32(priv, 0x404460, 0x0);

	nv_wr32(priv, 0x404464, 0x0);
@@ -2339,12 +2401,26 @@ nve0_graph_generate_unk5bxx(struct nvc0_graph_priv *priv) 
{

	nv_wr32(priv, 0x405b00, 0x0);

	nv_wr32(priv, 0x405b10, 0x1000);

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x405b20, 0x04000000);

		break;

	default:

		break;

	}

}



static void

nve0_graph_generate_unk60xx(struct nvc0_graph_priv *priv)

{

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x406020, 0x34103c1);

		break;

	default:

		nv_wr32(priv, 0x406020, 0x4103c1);

		break;

	}

	nv_wr32(priv, 0x406028, 0x1);

	nv_wr32(priv, 0x40602c, 0x1);

	nv_wr32(priv, 0x406030, 0x1);
@@ -2356,11 +2432,27 @@ nve0_graph_generate_unk64xx(struct nvc0_graph_priv *priv) 
{

	nv_wr32(priv, 0x4064a8, 0x0);

	nv_wr32(priv, 0x4064ac, 0x3fff);

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x4064b0, 0x0);

		break;

	default:

		break;

	}

	nv_wr32(priv, 0x4064b4, 0x0);

	nv_wr32(priv, 0x4064b8, 0x0);

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x4064c0, 0x802000f0);

		nv_wr32(priv, 0x4064c4, 0x192ffff);

		nv_wr32(priv, 0x4064c8, 0x18007c0);

		break;

	default:

		nv_wr32(priv, 0x4064c0, 0x801a00f0);

		nv_wr32(priv, 0x4064c4, 0x192ffff);

		nv_wr32(priv, 0x4064c8, 0x1800600);

		break;

	}

	nv_wr32(priv, 0x4064cc, 0x0);

	nv_wr32(priv, 0x4064d0, 0x0);

	nv_wr32(priv, 0x4064d4, 0x0);
@@ -2376,7 +2468,13 @@ nve0_graph_generate_unk64xx(struct nvc0_graph_priv *priv) 
static void

nve0_graph_generate_unk70xx(struct nvc0_graph_priv *priv)

{

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		break;

	default:

		nv_wr32(priv, 0x407040, 0x0);

		break;

	}

}



static void
@@ -2408,9 +2506,23 @@ nve0_graph_generate_unk80xx(struct nvc0_graph_priv *priv) 
static void

nve0_graph_generate_unk88xx(struct nvc0_graph_priv *priv)

{

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x408800, 0x12802a3c);

		break;

	default:

		nv_wr32(priv, 0x408800, 0x2802a3c);

		break;

	}

	nv_wr32(priv, 0x408804, 0x40);

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x408808, 0x1003e005);

		break;

	default:

		nv_wr32(priv, 0x408808, 0x1043e005);

		break;

	}

	nv_wr32(priv, 0x408840, 0xb);

	nv_wr32(priv, 0x408900, 0x3080b801);

	nv_wr32(priv, 0x408904, 0x62000001);
@@ -2447,7 +2559,14 @@ nve0_graph_generate_gpc(struct nvc0_graph_priv *priv) 
	nv_wr32(priv, 0x418710, 0x0);

	nv_wr32(priv, 0x418800, 0x7006860a);

	nv_wr32(priv, 0x418808, 0x0);

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x41880c, 0x30);

		break;

	default:

		nv_wr32(priv, 0x41880c, 0x0);

		break;

	}

	nv_wr32(priv, 0x418810, 0x0);

	nv_wr32(priv, 0x418828, 0x44);

	nv_wr32(priv, 0x418830, 0x10000001);
@@ -2493,6 +2612,13 @@ nve0_graph_generate_gpc(struct nvc0_graph_priv *priv) 
	nv_wr32(priv, 0x418c6c, 0x1);

	nv_wr32(priv, 0x418c80, 0x20200004);

	nv_wr32(priv, 0x418c8c, 0x1);

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x418d24, 0x0);

		break;

	default:

		break;

	}

	nv_wr32(priv, 0x419000, 0x780);

	nv_wr32(priv, 0x419004, 0x0);

	nv_wr32(priv, 0x419008, 0x0);
@@ -2512,31 +2638,71 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv) 
	nv_wr32(priv, 0x419a10, 0x0);

	nv_wr32(priv, 0x419a14, 0x200);

	nv_wr32(priv, 0x419a1c, 0xc000);

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x419a20, 0x20800);

		break;

	default:

		nv_wr32(priv, 0x419a20, 0x800);

		break;

	}

	nv_wr32(priv, 0x419a30, 0x1);

	nv_wr32(priv, 0x419ac4, 0x37f440);

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x419c00, 0x1a);

		break;

	default:

		nv_wr32(priv, 0x419c00, 0xa);

		break;

	}

	nv_wr32(priv, 0x419c04, 0x80000006);

	nv_wr32(priv, 0x419c08, 0x2);

	nv_wr32(priv, 0x419c20, 0x0);

	nv_wr32(priv, 0x419c24, 0x84210);

	nv_wr32(priv, 0x419c28, 0x3efbefbe);

	nv_wr32(priv, 0x419ce8, 0x0);

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x419cf4, 0x203);

		nv_wr32(priv, 0x419e04, 0x0);

		nv_wr32(priv, 0x419e08, 0x1d);

		nv_wr32(priv, 0x419e0c, 0x0);

		nv_wr32(priv, 0x419e10, 0x1c02);



		break;

	default:

		nv_wr32(priv, 0x419cf4, 0x3203);

		nv_wr32(priv, 0x419e04, 0x0);

		nv_wr32(priv, 0x419e08, 0x0);

		nv_wr32(priv, 0x419e0c, 0x0);

		nv_wr32(priv, 0x419e10, 0x402);

		break;

	}

	nv_wr32(priv, 0x419e44, 0x13eff2);

	nv_wr32(priv, 0x419e48, 0x0);

	nv_wr32(priv, 0x419e4c, 0x7f);

	nv_wr32(priv, 0x419e50, 0x0);

	nv_wr32(priv, 0x419e54, 0x0);

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x419e58, 0x1);

		break;

	default:

		nv_wr32(priv, 0x419e58, 0x0);

		break;

	}

	nv_wr32(priv, 0x419e5c, 0x0);

	nv_wr32(priv, 0x419e60, 0x0);

	nv_wr32(priv, 0x419e64, 0x0);

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x419e68, 0x2);

		break;

	default:

		nv_wr32(priv, 0x419e68, 0x0);

		break;

	}

	nv_wr32(priv, 0x419e6c, 0x0);

	nv_wr32(priv, 0x419e70, 0x0);

	nv_wr32(priv, 0x419e74, 0x0);
@@ -2553,18 +2719,31 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv) 
	case 0xe7:

	case 0xe6:

		nv_wr32(priv, 0x419eac, 0x1f8f);

		nv_wr32(priv, 0x419eb0, 0xd3f);

		break;

	case 0xf0:

		nv_wr32(priv, 0x419eac, 0x1fcf);

		nv_wr32(priv, 0x419eb0, 0xdb00da0);

		nv_wr32(priv, 0x419eb8, 0x0);

		break;

	default:

		nv_wr32(priv, 0x419eac, 0x1fcf);

		nv_wr32(priv, 0x419eb0, 0xd3f);

		break;

	}

	nv_wr32(priv, 0x419eb0, 0xd3f);

	nv_wr32(priv, 0x419ec8, 0x1304f);

	nv_wr32(priv, 0x419f30, 0x0);

	nv_wr32(priv, 0x419f34, 0x0);

	nv_wr32(priv, 0x419f38, 0x0);

	nv_wr32(priv, 0x419f3c, 0x0);

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x419f40, 0x18);

		break;

	default:

		nv_wr32(priv, 0x419f40, 0x0);

		break;

	}

	nv_wr32(priv, 0x419f44, 0x0);

	nv_wr32(priv, 0x419f48, 0x0);

	nv_wr32(priv, 0x419f4c, 0x0);
@@ -2573,17 +2752,16 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv) 
	case 0xe7:

	case 0xe6:

		nv_wr32(priv, 0x419f70, 0x0);

		break;

	default:

		break;

	}

		nv_wr32(priv, 0x419f78, 0xb);

	switch (nv_device(priv)->chipset) {

	case 0xe7:

	case 0xe6:

		nv_wr32(priv, 0x419f7c, 0x27a);

		break;

	case 0xf0:

		nv_wr32(priv, 0x419f70, 0x7300);

		nv_wr32(priv, 0x419f78, 0xeb);

		nv_wr32(priv, 0x419f7c, 0x404);

		break;

	default:

		nv_wr32(priv, 0x419f78, 0xb);

		break;

	}

}
@@ -2592,9 +2770,23 @@ static void 
nve0_graph_generate_tpcunk(struct nvc0_graph_priv *priv)

{

	nv_wr32(priv, 0x41be24, 0x6);

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x41bec0, 0x10000000);

		break;

	default:

		nv_wr32(priv, 0x41bec0, 0x12180000);

		break;

	}

	nv_wr32(priv, 0x41bec4, 0x37f7f);

	switch (nv_device(priv)->chipset) {

	case 0xf0:

		nv_wr32(priv, 0x41bee4, 0x0);

		break;

	default:

		nv_wr32(priv, 0x41bee4, 0x6480430);

		break;

	}

	nv_wr32(priv, 0x41bf00, 0xa418820);

	nv_wr32(priv, 0x41bf04, 0x62080e6);

	nv_wr32(priv, 0x41bf08, 0x20398a4);

drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc

+59 −0
Original line number Diff line number Diff line
@@ -62,6 +62,11 @@ chipsets: 
.b16 #nve4_gpc_mmio_tail

.b16 #nve6_tpc_mmio_head

.b16 #nve6_tpc_mmio_tail

.b8  0xf0 0 0 0

.b16 #nvf0_gpc_mmio_head

.b16 #nvf0_gpc_mmio_tail

.b16 #nvf0_tpc_mmio_head

.b16 #nvf0_tpc_mmio_tail

.b8  0 0 0 0



// GPC mmio lists
@@ -101,6 +106,37 @@ mmctx_data(0x0031d0, 1) 
mmctx_data(0x0031e0, 2)

nve4_gpc_mmio_tail:



nvf0_gpc_mmio_head:

mmctx_data(0x000380, 1)

mmctx_data(0x000400, 2)

mmctx_data(0x00040c, 3)

mmctx_data(0x000450, 9)

mmctx_data(0x000600, 1)

mmctx_data(0x000684, 1)

mmctx_data(0x000700, 5)

mmctx_data(0x000800, 1)

mmctx_data(0x000808, 3)

mmctx_data(0x000828, 1)

mmctx_data(0x000830, 1)

mmctx_data(0x0008d8, 1)

mmctx_data(0x0008e0, 1)

mmctx_data(0x0008e8, 6)

mmctx_data(0x00091c, 1)

mmctx_data(0x000924, 3)

mmctx_data(0x000b00, 1)

mmctx_data(0x000b08, 6)

mmctx_data(0x000bb8, 1)

mmctx_data(0x000c08, 1)

mmctx_data(0x000c10, 8)

mmctx_data(0x000c40, 1)

mmctx_data(0x000c6c, 1)

mmctx_data(0x000c80, 1)

mmctx_data(0x000c8c, 1)

mmctx_data(0x000d24, 1)

mmctx_data(0x001000, 3)

mmctx_data(0x001014, 1)

nvf0_gpc_mmio_tail:



// TPC mmio lists

nve4_tpc_mmio_head:

mmctx_data(0x000048, 1)
@@ -145,6 +181,29 @@ mmctx_data(0x000770, 1) 
mmctx_data(0x000778, 2)

nve6_tpc_mmio_tail:



nvf0_tpc_mmio_head:

mmctx_data(0x000048, 1)

mmctx_data(0x000064, 1)

mmctx_data(0x000088, 1)

mmctx_data(0x000200, 6)

mmctx_data(0x00021c, 2)

mmctx_data(0x000230, 1)

mmctx_data(0x0002c4, 1)

mmctx_data(0x000400, 3)

mmctx_data(0x000420, 3)

mmctx_data(0x0004e8, 1)

mmctx_data(0x0004f4, 1)

mmctx_data(0x000604, 4)

mmctx_data(0x000644, 22)

mmctx_data(0x0006ac, 2)

mmctx_data(0x0006b8, 1)

mmctx_data(0x0006c8, 1)

mmctx_data(0x000730, 8)

mmctx_data(0x000758, 1)

mmctx_data(0x000770, 1)

mmctx_data(0x000778, 2)

nvf0_tpc_mmio_tail:



.section #nve0_grgpc_code

bra #init

define(`include_code')

drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h

+66 −11
Original line number Diff line number Diff line
@@ -34,16 +34,19 @@ uint32_t nve0_grgpc_data[] = { 
	0x00000000,

/* 0x0064: chipsets */

	0x000000e4,

	0x0110008c,

	0x01580110,

	0x011c0098,

	0x01d4018c,

	0x000000e7,

	0x0110008c,

	0x01a40158,

	0x011c0098,

	0x022001d4,

	0x000000e6,

	0x0110008c,

	0x01a40158,

	0x011c0098,

	0x022001d4,

	0x000000f0,

	0x018c011c,

	0x02700220,

	0x00000000,

/* 0x008c: nve4_gpc_mmio_head */

/* 0x0098: nve4_gpc_mmio_head */

	0x00000380,

	0x04000400,

	0x0800040c,
@@ -77,8 +80,38 @@ uint32_t nve0_grgpc_data[] = { 
	0x14003100,

	0x000031d0,

	0x040031e0,

/* 0x0110: nve4_gpc_mmio_tail */

/* 0x0110: nve4_tpc_mmio_head */

/* 0x011c: nve4_gpc_mmio_tail */

/* 0x011c: nvf0_gpc_mmio_head */

	0x00000380,

	0x04000400,

	0x0800040c,

	0x20000450,

	0x00000600,

	0x00000684,

	0x10000700,

	0x00000800,

	0x08000808,

	0x00000828,

	0x00000830,

	0x000008d8,

	0x000008e0,

	0x140008e8,

	0x0000091c,

	0x08000924,

	0x00000b00,

	0x14000b08,

	0x00000bb8,

	0x00000c08,

	0x1c000c10,

	0x00000c40,

	0x00000c6c,

	0x00000c80,

	0x00000c8c,

	0x00000d24,

	0x08001000,

	0x00001014,

/* 0x018c: nvf0_gpc_mmio_tail */

/* 0x018c: nve4_tpc_mmio_head */

	0x00000048,

	0x00000064,

	0x00000088,
@@ -97,8 +130,29 @@ uint32_t nve0_grgpc_data[] = { 
	0x1c000730,

	0x00000758,

	0x00000778,

/* 0x0158: nve4_tpc_mmio_tail */

/* 0x0158: nve6_tpc_mmio_head */

/* 0x01d4: nve4_tpc_mmio_tail */

/* 0x01d4: nve6_tpc_mmio_head */

	0x00000048,

	0x00000064,

	0x00000088,

	0x14000200,

	0x0400021c,

	0x00000230,

	0x000002c4,

	0x08000400,

	0x08000420,

	0x000004e8,

	0x000004f4,

	0x0c000604,

	0x54000644,

	0x040006ac,

	0x000006c8,

	0x1c000730,

	0x00000758,

	0x00000770,

	0x04000778,

/* 0x0220: nve6_tpc_mmio_tail */

/* 0x0220: nvf0_tpc_mmio_head */

	0x00000048,

	0x00000064,

	0x00000088,
@@ -113,6 +167,7 @@ uint32_t nve0_grgpc_data[] = { 
	0x0c000604,

	0x54000644,

	0x040006ac,

	0x000006b8,

	0x000006c8,

	0x1c000730,

	0x00000758,

drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc

+67 −7
Original line number Diff line number Diff line
@@ -37,6 +37,15 @@ hub_mmio_list_tail: .b32 0 


ctx_current:		.b32 0



.align 256

chan_data:

chan_mmio_count:	.b32 0

chan_mmio_address:	.b32 0



.align 256

xfer_data: 		.b32 0



.align 256

chipsets:

.b8  0xe4 0 0 0

.b16 #nve4_hub_mmio_head
@@ -47,6 +56,9 @@ chipsets: 
.b8  0xe6 0 0 0

.b16 #nve4_hub_mmio_head

.b16 #nve4_hub_mmio_tail

.b8  0xf0 0 0 0

.b16 #nvf0_hub_mmio_head

.b16 #nvf0_hub_mmio_tail

.b8  0 0 0 0



nve4_hub_mmio_head:
@@ -103,13 +115,61 @@ mmctx_data(0x408900, 3) 
mmctx_data(0x408980, 1)

nve4_hub_mmio_tail:



.align 256

chan_data:

chan_mmio_count:	.b32 0

chan_mmio_address:	.b32 0



.align 256

xfer_data: 		.b32 0

nvf0_hub_mmio_head:

mmctx_data(0x17e91c, 2)

mmctx_data(0x400204, 2)

mmctx_data(0x404004, 17)

mmctx_data(0x4040a8, 9)

mmctx_data(0x4040d0, 7)

mmctx_data(0x4040f8, 1)

mmctx_data(0x404100, 10)

mmctx_data(0x404130, 3)

mmctx_data(0x404150, 3)

mmctx_data(0x404164, 1)

mmctx_data(0x40417c, 2)

mmctx_data(0x4041a0, 4)

mmctx_data(0x404200, 4)

mmctx_data(0x404404, 12)

mmctx_data(0x404438, 1)

mmctx_data(0x404460, 4)

mmctx_data(0x404480, 1)

mmctx_data(0x404498, 1)

mmctx_data(0x404604, 4)

mmctx_data(0x404618, 4)

mmctx_data(0x40462c, 2)

mmctx_data(0x404640, 1)

mmctx_data(0x404654, 1)

mmctx_data(0x404660, 1)

mmctx_data(0x404678, 19)

mmctx_data(0x4046c8, 3)

mmctx_data(0x404700, 3)

mmctx_data(0x404718, 10)

mmctx_data(0x404744, 2)

mmctx_data(0x404754, 1)

mmctx_data(0x405800, 1)

mmctx_data(0x405830, 3)

mmctx_data(0x405854, 1)

mmctx_data(0x405870, 4)

mmctx_data(0x405a00, 2)

mmctx_data(0x405a18, 1)

mmctx_data(0x405b00, 1)

mmctx_data(0x405b10, 1)

mmctx_data(0x405b20, 1)

mmctx_data(0x406020, 1)

mmctx_data(0x406028, 4)

mmctx_data(0x4064a8, 5)

mmctx_data(0x4064c0, 12)

mmctx_data(0x4064fc, 1)

mmctx_data(0x407804, 1)

mmctx_data(0x40780c, 6)

mmctx_data(0x4078bc, 1)

mmctx_data(0x408000, 7)

mmctx_data(0x408064, 1)

mmctx_data(0x408800, 3)

mmctx_data(0x408840, 1)

mmctx_data(0x408900, 3)

mmctx_data(0x408980, 1)

nvf0_hub_mmio_tail:



.section #nve0_grhub_code

bra #init

drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h

+534 −421

File changed.

Preview size limit exceeded, changes collapsed.