Merge "clk: qcom: gcc-sdxpoorwills: add GCC_SYS_NOC_USB3_CLK clock" into msm-4.9

#define GCC_SPMI_FETCHER_CLK					65

#define GCC_SPMI_FETCHER_CLK_SRC				66

#define GCC_SYS_NOC_CPUSS_AHB_CLK				67

#define GCC_USB30_MASTER_CLK					68

#define GCC_USB30_MASTER_CLK_SRC				69

#define GCC_USB30_MOCK_UTMI_CLK					70

#define GCC_USB30_MOCK_UTMI_CLK_SRC				71

#define GCC_USB30_SLEEP_CLK					72

#define GCC_USB3_PRIM_CLKREF_CLK				73

#define GCC_USB3_PHY_AUX_CLK					74

#define GCC_USB3_PHY_AUX_CLK_SRC				75

#define GCC_USB3_PHY_PIPE_CLK					76

#define GCC_USB_PHY_CFG_AHB2PHY_CLK				77

#define GCC_XO_DIV4_CLK						78

#define GPLL0							79

#define GPLL0_OUT_EVEN						80

#define GCC_SYS_NOC_USB3_CLK					68

#define GCC_USB30_MASTER_CLK					69

#define GCC_USB30_MASTER_CLK_SRC				70

#define GCC_USB30_MOCK_UTMI_CLK					71

#define GCC_USB30_MOCK_UTMI_CLK_SRC				72

#define GCC_USB30_SLEEP_CLK					73

#define GCC_USB3_PRIM_CLKREF_CLK				74

#define GCC_USB3_PHY_AUX_CLK					75

#define GCC_USB3_PHY_AUX_CLK_SRC				76

#define GCC_USB3_PHY_PIPE_CLK					77

#define GCC_USB_PHY_CFG_AHB2PHY_CLK				78

#define GCC_XO_DIV4_CLK						79

#define GPLL0							80

#define GPLL0_OUT_EVEN						81

/* GDSCs */

#define PCIE_GDSC						0