Merge "arm64: SW PAN: Update saved ttbr0 value on enter_lazy_tlb" (cabf1705) · Commits · e / devices / android_kernel_fairphone_FP3

arch/arm64/include/asm/mmu_context.h

+10 −14

Original line number	Diff line number	Diff line
		@@ -156,20 +156,6 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu);

		#define init_new_context(tsk,mm) ({ atomic64_set(&(mm)->context.id, 0); 0; })

		/*
		* This is called when "tsk" is about to enter lazy TLB mode.
		*
		* mm: describes the currently active mm context
		* tsk: task which is entering lazy tlb
		* cpu: cpu number which is entering lazy tlb
		*
		* tsk->mm will be NULL
		*/
		static inline void
		enter_lazy_tlb(struct mm_struct mm, struct task_struct tsk)
		{
		}

		#ifdef CONFIG_ARM64_SW_TTBR0_PAN
		static inline void update_saved_ttbr0(struct task_struct *tsk,
		struct mm_struct *mm)
		@@ -193,6 +179,16 @@ static inline void update_saved_ttbr0(struct task_struct *tsk,
		}
		#endif

		static inline void
		enter_lazy_tlb(struct mm_struct mm, struct task_struct tsk)
		{
		/*
		* We don't actually care about the ttbr0 mapping, so point it at the
		* zero page.
		*/
		update_saved_ttbr0(tsk, &init_mm);
		}

		static inline void __switch_mm(struct mm_struct *next)
		{
		unsigned int cpu = smp_processor_id();