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Commit ca585cf9 authored by Kelvin Cheung's avatar Kelvin Cheung Committed by Ralf Baechle
Browse files

MIPS: Loongson 1B: Add board support 



Adds basic platform devices for Loongson 1B, including serial port,
ethernet, USB, RTC and interrupt handler.

The Loongson 1B UART is compatible with NS16550A, the Loongson 1B GMAC is
built around a Synopsys IP Core.

Use normal instead of enhanced descriptors.

Thanks to Giuseppe for updating the normal descriptor in stmmac driver.
Thanks to Zhao Zhang for implementing the RTC driver.

Signed-off-by: default avatarKelvin Cheung <keguang.zhang@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: wuzhangjin@gmail.com
Cc: zhzhl555@gmail.com
Cc: Kelvin Cheung <keguang.zhang@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/4133/
Patchwork: https://patchwork.linux-mips.org/patch/4134/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 2fa36399

arch/mips/Kbuild.platforms

+1 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ platforms += jz4740 
platforms += lantiq

platforms += lasat

platforms += loongson

platforms += loongson1

platforms += mipssim

platforms += mti-malta

platforms += netlogic

arch/mips/Kconfig

+30 −0
Original line number Diff line number Diff line
@@ -264,6 +264,16 @@ config MACH_LOONGSON 
	  Chinese Academy of Sciences (CAS) in the People's Republic

	  of China. The chief architect is Professor Weiwu Hu.



config MACH_LOONGSON1

	bool "Loongson 1 family of machines"

	select SYS_SUPPORTS_ZBOOT

	help

	  This enables support for the Loongson 1 based machines.



	  Loongson 1 is a family of 32-bit MIPS-compatible SoCs developed by

	  the ICT (Institute of Computing Technology) and the Chinese Academy

	  of Sciences.



config MIPS_MALTA

	bool "MIPS Malta board"

	select ARCH_MAY_HAVE_PC_FDC
@@ -836,6 +846,7 @@ source "arch/mips/txx9/Kconfig" 
source "arch/mips/vr41xx/Kconfig"

source "arch/mips/cavium-octeon/Kconfig"

source "arch/mips/loongson/Kconfig"

source "arch/mips/loongson1/Kconfig"

source "arch/mips/netlogic/Kconfig"



endmenu
@@ -1217,6 +1228,14 @@ config CPU_LOONGSON2F 
	  have a similar programming interface with FPGA northbridge used in

	  Loongson2E.



config CPU_LOONGSON1B

	bool "Loongson 1B"

	depends on SYS_HAS_CPU_LOONGSON1B

	select CPU_LOONGSON1

	help

	  The Loongson 1B is a 32-bit SoC, which implements the MIPS32

	  release 2 instruction set.



config CPU_MIPS32_R1

	bool "MIPS32 Release 1"

	depends on SYS_HAS_CPU_MIPS32_R1
@@ -1544,6 +1563,14 @@ config CPU_LOONGSON2 
	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM



config CPU_LOONGSON1

	bool

	select CPU_MIPS32

	select CPU_MIPSR2

	select CPU_HAS_PREFETCH

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM



config CPU_BMIPS

	bool

	select CPU_MIPS32
@@ -1562,6 +1589,9 @@ config SYS_HAS_CPU_LOONGSON2F 
	select CPU_SUPPORTS_ADDRWINCFG if 64BIT

	select CPU_SUPPORTS_UNCACHED_ACCELERATED



config SYS_HAS_CPU_LOONGSON1B

	bool



config SYS_HAS_CPU_MIPS32_R1

	bool

arch/mips/include/asm/mach-loongson1/irq.h

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+73 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>

 *

 * IRQ mappings for Loongson 1

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */





#ifndef __ASM_MACH_LOONGSON1_IRQ_H

#define __ASM_MACH_LOONGSON1_IRQ_H



/*

 * CPU core Interrupt Numbers

 */

#define MIPS_CPU_IRQ_BASE		0

#define MIPS_CPU_IRQ(x)			(MIPS_CPU_IRQ_BASE + (x))



#define SOFTINT0_IRQ			MIPS_CPU_IRQ(0)

#define SOFTINT1_IRQ			MIPS_CPU_IRQ(1)

#define INT0_IRQ			MIPS_CPU_IRQ(2)

#define INT1_IRQ			MIPS_CPU_IRQ(3)

#define INT2_IRQ			MIPS_CPU_IRQ(4)

#define INT3_IRQ			MIPS_CPU_IRQ(5)

#define INT4_IRQ			MIPS_CPU_IRQ(6)

#define TIMER_IRQ			MIPS_CPU_IRQ(7)		/* cpu timer */



#define MIPS_CPU_IRQS		(MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)



/*

 * INT0~3 Interrupt Numbers

 */

#define LS1X_IRQ_BASE			MIPS_CPU_IRQS

#define LS1X_IRQ(n, x)			(LS1X_IRQ_BASE + (n << 5) + (x))



#define LS1X_UART0_IRQ			LS1X_IRQ(0, 2)

#define LS1X_UART1_IRQ			LS1X_IRQ(0, 3)

#define LS1X_UART2_IRQ			LS1X_IRQ(0, 4)

#define LS1X_UART3_IRQ			LS1X_IRQ(0, 5)

#define LS1X_CAN0_IRQ			LS1X_IRQ(0, 6)

#define LS1X_CAN1_IRQ			LS1X_IRQ(0, 7)

#define LS1X_SPI0_IRQ			LS1X_IRQ(0, 8)

#define LS1X_SPI1_IRQ			LS1X_IRQ(0, 9)

#define LS1X_AC97_IRQ			LS1X_IRQ(0, 10)

#define LS1X_DMA0_IRQ			LS1X_IRQ(0, 13)

#define LS1X_DMA1_IRQ			LS1X_IRQ(0, 14)

#define LS1X_DMA2_IRQ			LS1X_IRQ(0, 15)

#define LS1X_PWM0_IRQ			LS1X_IRQ(0, 17)

#define LS1X_PWM1_IRQ			LS1X_IRQ(0, 18)

#define LS1X_PWM2_IRQ			LS1X_IRQ(0, 19)

#define LS1X_PWM3_IRQ			LS1X_IRQ(0, 20)

#define LS1X_RTC_INT0_IRQ		LS1X_IRQ(0, 21)

#define LS1X_RTC_INT1_IRQ		LS1X_IRQ(0, 22)

#define LS1X_RTC_INT2_IRQ		LS1X_IRQ(0, 23)

#define LS1X_TOY_INT0_IRQ		LS1X_IRQ(0, 24)

#define LS1X_TOY_INT1_IRQ		LS1X_IRQ(0, 25)

#define LS1X_TOY_INT2_IRQ		LS1X_IRQ(0, 26)

#define LS1X_RTC_TICK_IRQ		LS1X_IRQ(0, 27)

#define LS1X_TOY_TICK_IRQ		LS1X_IRQ(0, 28)



#define LS1X_EHCI_IRQ			LS1X_IRQ(1, 0)

#define LS1X_OHCI_IRQ			LS1X_IRQ(1, 1)

#define LS1X_GMAC0_IRQ			LS1X_IRQ(1, 2)

#define LS1X_GMAC1_IRQ			LS1X_IRQ(1, 3)



#define LS1X_IRQS		(LS1X_IRQ(4, 31) + 1 - LS1X_IRQ_BASE)



#define NR_IRQS			(MIPS_CPU_IRQS + LS1X_IRQS)



#endif /* __ASM_MACH_LOONGSON1_IRQ_H */

arch/mips/include/asm/mach-loongson1/loongson1.h

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+44 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>

 *

 * Register mappings for Loongson 1

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */





#ifndef __ASM_MACH_LOONGSON1_LOONGSON1_H

#define __ASM_MACH_LOONGSON1_LOONGSON1_H



#define DEFAULT_MEMSIZE			256	/* If no memsize provided */



/* Loongson 1 Register Bases */

#define LS1X_INTC_BASE			0x1fd01040

#define LS1X_EHCI_BASE			0x1fe00000

#define LS1X_OHCI_BASE			0x1fe08000

#define LS1X_GMAC0_BASE			0x1fe10000

#define LS1X_GMAC1_BASE			0x1fe20000



#define LS1X_UART0_BASE			0x1fe40000

#define LS1X_UART1_BASE			0x1fe44000

#define LS1X_UART2_BASE			0x1fe48000

#define LS1X_UART3_BASE			0x1fe4c000

#define LS1X_CAN0_BASE			0x1fe50000

#define LS1X_CAN1_BASE			0x1fe54000

#define LS1X_I2C0_BASE			0x1fe58000

#define LS1X_I2C1_BASE			0x1fe68000

#define LS1X_I2C2_BASE			0x1fe70000

#define LS1X_PWM_BASE			0x1fe5c000

#define LS1X_WDT_BASE			0x1fe5c060

#define LS1X_RTC_BASE			0x1fe64000

#define LS1X_AC97_BASE			0x1fe74000

#define LS1X_NAND_BASE			0x1fe78000

#define LS1X_CLK_BASE			0x1fe78030



#include <regs-clk.h>

#include <regs-wdt.h>



#endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */

arch/mips/include/asm/mach-loongson1/platform.h

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+23 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */





#ifndef __ASM_MACH_LOONGSON1_PLATFORM_H

#define __ASM_MACH_LOONGSON1_PLATFORM_H



#include <linux/platform_device.h>



extern struct platform_device ls1x_uart_device;

extern struct platform_device ls1x_eth0_device;

extern struct platform_device ls1x_ehci_device;

extern struct platform_device ls1x_rtc_device;



void ls1x_serial_setup(void);



#endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */