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Commit ca2ac5cc authored by Andrew Lunn's avatar Andrew Lunn
Browse files

Dove: Fix Section mismatch warnings 



Add missing __init markups to GPIO and timer functions.

Signed-off-by: default avatarAndrew Lunn <andrew@lunn.ch>
parent 4d72cef1

arch/arm/mach-dove/common.c

+1 −1
Original line number Diff line number Diff line
@@ -181,7 +181,7 @@ static int get_tclk(void) 
	return 166666667;

}



static void dove_timer_init(void)

static void __init dove_timer_init(void)

{

	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,

			IRQ_DOVE_BRIDGE, get_tclk());

arch/arm/mach-dove/mpp.c

+4 −4
Original line number Diff line number Diff line
@@ -56,7 +56,7 @@ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode) 


/* Dump all the extra MPP registers. The platform code will dump the

   registers for pins 0-23. */

static void dove_mpp_dump_regs(void)

static void __init dove_mpp_dump_regs(void)

{

	pr_debug("PMU_CTRL4_CTRL: %08x\n",

		 readl(DOVE_MPP_CTRL4_VIRT_BASE));
@@ -67,7 +67,7 @@ static void dove_mpp_dump_regs(void) 
	pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));

}



static void dove_mpp_cfg_nfc(int sel)

static void __init dove_mpp_cfg_nfc(int sel)

{

	u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE);
@@ -78,7 +78,7 @@ static void dove_mpp_cfg_nfc(int sel) 
	dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK);

}



static void dove_mpp_cfg_au1(int sel)

static void __init dove_mpp_cfg_au1(int sel)

{

	u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);

	u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
@@ -118,7 +118,7 @@ static void dove_mpp_cfg_au1(int sel) 


/* Configure the group registers, enabling GPIO if sel indicates the

   pin is to be used for GPIO */

static void dove_mpp_conf_grp(unsigned int *mpp_grp_list)

static void __init dove_mpp_conf_grp(unsigned int *mpp_grp_list)

{

	u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);

	int gpio_mode;