Merge "msm: kgsl: Add quirk support to use alternative secure context bank" (c95ae033) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/devicetree/bindings/gpu/adreno-iommu.txt

+6 −0

Original line number	Original line	Diff line number	Diff line
	@@ -42,6 +42,7 @@ Optional properties:
	currently supported names are:		currently supported names are:
	- gfx3d_user : Used for the 'normal' GPU address space.		- gfx3d_user : Used for the 'normal' GPU address space.
	- gfx3d_secure : Used for the content protection address space.		- gfx3d_secure : Used for the content protection address space.
			- gfx3d_secure_alt : Used for the content protection address space for alternative SID.
	Each sub node has the following required properties:		Each sub node has the following required properties:

	- compatible : "qcom,smmu-kgsl-cb"		- compatible : "qcom,smmu-kgsl-cb"
	@@ -83,4 +84,9 @@ Example:
	compatible = "qcom,smmu-kgsl-cb";		compatible = "qcom,smmu-kgsl-cb";
	iommus = <&kgsl_smmu 2>;		iommus = <&kgsl_smmu 2>;
	};		};

			gfx3d_secure_alt: gfx3d_secure_alt {
			compatible = "qcom,smmu-kgsl-cb";
			iommus = <&kgsl_smmu 2>, <&kgsl_smmu 1>;
			};
	};		};

Documentation/devicetree/bindings/gpu/adreno.txt

+3 −0

Original line number	Original line	Diff line number	Diff line
	@@ -207,6 +207,9 @@ GPU Quirks:
	- qcom,gpu-quirk-limit-uche-gbif-rw:		- qcom,gpu-quirk-limit-uche-gbif-rw:
	Limit number of read and write transactions from UCHE block to		Limit number of read and write transactions from UCHE block to
	GBIF to avoid possible deadlock between GBIF, SMMU and MEMNOC.		GBIF to avoid possible deadlock between GBIF, SMMU and MEMNOC.
			- qcom,gpu-quirk-mmu-secure-cb-alt:
			Select alternate secure context bank to generate SID1 for
			secure playback.

	KGSL Memory Pools:		KGSL Memory Pools:
	- qcom,gpu-mempools: Container for sets of GPU mempools.Multiple sets		- qcom,gpu-mempools: Container for sets of GPU mempools.Multiple sets

drivers/gpu/msm/adreno.c

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -744,6 +744,7 @@ static struct {
	{ ADRENO_QUIRK_SECVID_SET_ONCE, "qcom,gpu-quirk-secvid-set-once" },		{ ADRENO_QUIRK_SECVID_SET_ONCE, "qcom,gpu-quirk-secvid-set-once" },
	{ ADRENO_QUIRK_LIMIT_UCHE_GBIF_RW,		{ ADRENO_QUIRK_LIMIT_UCHE_GBIF_RW,
	"qcom,gpu-quirk-limit-uche-gbif-rw" },		"qcom,gpu-quirk-limit-uche-gbif-rw" },
			{ ADRENO_QUIRK_MMU_SECURE_CB_ALT, "qcom,gpu-quirk-mmu-secure-cb-alt" },
	};		};

	static struct device_node *		static struct device_node *

drivers/gpu/msm/adreno.h

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -150,6 +150,8 @@
	* between GBIF, SMMU and MEMNOC.		* between GBIF, SMMU and MEMNOC.
	*/		*/
	#define ADRENO_QUIRK_LIMIT_UCHE_GBIF_RW BIT(8)		#define ADRENO_QUIRK_LIMIT_UCHE_GBIF_RW BIT(8)
			/* Select alternate secure context bank for mmu */
			#define ADRENO_QUIRK_MMU_SECURE_CB_ALT BIT(9)

	/* Flags to control command packet settings */		/* Flags to control command packet settings */
	#define KGSL_CMD_FLAGS_NONE 0		#define KGSL_CMD_FLAGS_NONE 0

drivers/gpu/msm/kgsl_iommu.c

+11 −2

Original line number	Original line	Diff line number	Diff line
	@@ -2527,6 +2527,7 @@ static const struct {
	} kgsl_iommu_cbs[] = {		} kgsl_iommu_cbs[] = {
	{ KGSL_IOMMU_CONTEXT_USER, "gfx3d_user", },		{ KGSL_IOMMU_CONTEXT_USER, "gfx3d_user", },
	{ KGSL_IOMMU_CONTEXT_SECURE, "gfx3d_secure" },		{ KGSL_IOMMU_CONTEXT_SECURE, "gfx3d_secure" },
			{ KGSL_IOMMU_CONTEXT_SECURE, "gfx3d_secure_alt" },
	};		};

	static int _kgsl_iommu_cb_probe(struct kgsl_device *device,		static int _kgsl_iommu_cb_probe(struct kgsl_device *device,
	@@ -2534,12 +2535,20 @@ static int _kgsl_iommu_cb_probe(struct kgsl_device *device,
	{		{
	struct platform_device *pdev = of_find_device_by_node(node);		struct platform_device *pdev = of_find_device_by_node(node);
	struct kgsl_iommu_context *ctx = NULL;		struct kgsl_iommu_context *ctx = NULL;
			struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
	int i;		int i;

	for (i = 0; i < ARRAY_SIZE(kgsl_iommu_cbs); i++) {		for (i = 0; i < ARRAY_SIZE(kgsl_iommu_cbs); i++) {
	if (!strcmp(node->name, kgsl_iommu_cbs[i].name)) {		if (!strcmp(node->name, kgsl_iommu_cbs[i].name)) {
	int id = kgsl_iommu_cbs[i].id;		int id = kgsl_iommu_cbs[i].id;

			if (ADRENO_QUIRK(adreno_dev,
			ADRENO_QUIRK_MMU_SECURE_CB_ALT)) {
			if (!strcmp(node->name, "gfx3d_secure"))
			continue;
			} else if (!strcmp(node->name, "gfx3d_secure_alt"))
			continue;

	ctx = &iommu->ctx[id];		ctx = &iommu->ctx[id];
	ctx->id = id;		ctx->id = id;
	ctx->cb_num = -1;		ctx->cb_num = -1;
	@@ -2550,8 +2559,8 @@ static int _kgsl_iommu_cb_probe(struct kgsl_device *device,
	}		}

	if (ctx == NULL) {		if (ctx == NULL) {
	KGSL_CORE_ERR("dt: Unknown context label %s\n", node->name);		KGSL_CORE_ERR("dt: Unused context label %s\n", node->name);
	return -EINVAL;		return 0;
	}		}

	if (ctx->id == KGSL_IOMMU_CONTEXT_SECURE)		if (ctx->id == KGSL_IOMMU_CONTEXT_SECURE)