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Commit c8e96269 authored by Karthik Anantha Ram's avatar Karthik Anantha Ram Committed by Gerrit - the friendly Code Review server
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msm: camera: icp: Reset pwr_ctrl register as part of PC 



Before we transfer control to ICP, APPs CPU needs to ensure
that pwr_ctrl register is not set.

Change-Id: I9e7315e45b0e2621953adb4da3f41af446dbaeb2
Signed-off-by: default avatarKarthik Anantha Ram <kartanan@codeaurora.org>
parent 1d8ba62c

drivers/media/platform/msm/camera/cam_icp/icp_hw/bps_hw/bps_core.c

+4 −2
Original line number Diff line number Diff line
@@ -199,8 +199,10 @@ static int cam_bps_handle_resume(struct cam_hw_info *bps_dev) 
	cam_cpas_reg_read(core_info->cpas_handle,

		CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, &pwr_ctrl);

	if (pwr_ctrl & BPS_COLLAPSE_MASK) {

		CAM_ERR(CAM_ICP, "BPS: pwr_ctrl(%x)", pwr_ctrl);

		return -EINVAL;

		CAM_WARN(CAM_ICP, "BPS: pwr_ctrl set(%x)", pwr_ctrl);

		cam_cpas_reg_write(core_info->cpas_handle,

			CAM_CPAS_REG_CPASTOP,

			hw_info->pwr_ctrl, true, 0);

	}



	rc = cam_bps_transfer_gdsc_control(soc_info);

drivers/media/platform/msm/camera/cam_icp/icp_hw/ipe_hw/ipe_core.c

+5 −2
Original line number Diff line number Diff line
@@ -195,9 +195,12 @@ static int cam_ipe_handle_resume(struct cam_hw_info *ipe_dev) 
		CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,

		true, &pwr_ctrl);

	if (pwr_ctrl & IPE_COLLAPSE_MASK) {

		CAM_ERR(CAM_ICP, "IPE: resume failed : %d", pwr_ctrl);

		return -EINVAL;

		CAM_WARN(CAM_ICP, "IPE pwr_ctrl set(%x)", pwr_ctrl);

		cam_cpas_reg_write(core_info->cpas_handle,

			CAM_CPAS_REG_CPASTOP,

			hw_info->pwr_ctrl, true, 0);

	}



	rc = cam_ipe_transfer_gdsc_control(soc_info);

	cam_cpas_reg_read(core_info->cpas_handle,

		CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, &pwr_ctrl);