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Commit c8d69e2a authored by Mayank Rana's avatar Mayank Rana
Browse files

ARM: dts: msm: Update USB QUSB2PHY initialization sequence for SDM845 



This change updates USB QUSB2PHY initialization sequence to get PHY
into operational state on SDM845.

Change-Id: I7a2868a9cb0d34ee87dab6d2856f0c41ccf92d38
Signed-off-by: default avatarMayank Rana <mrana@codeaurora.org>
parent 0f105b40

arch/arm64/boot/dts/qcom/sdm845-usb.dtsi

+40 −20
Original line number Diff line number Diff line
@@ -77,15 +77,25 @@ 
		qcom,vdd-voltage-level = <0 880000 880000>;

		qcom,qusb-phy-init-seq =

			/* <value reg_offset> */

					<0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */

			   <0x23 0x210 /* PWR_CTRL1 */

			    0x03 0x04  /* PLL_ANALOG_CONTROLS_TWO */

			    0x7c 0x18c /* PLL_CLOCK_INVERTERS */

			    0x80 0x2c  /* PLL_CMODE */

			    0x0a 0x184 /* PLL_LOCK_DELAY */

			    0x19 0xb4  /* PLL_DIGITAL_TIMERS_TWO */

					0xa5 0x240 /* TUNE1 */

					0x09 0x244 /* TUNE2 */

			    0x40 0x194 /* PLL_BIAS_CONTROL_1 */

			    0x20 0x198 /* PLL_BIAS_CONTROL_2 */

			    0x21 0x214 /* PWR_CTRL2 */

			    0x00 0x220 /* IMP_CTRL1 */

					0x58 0x224>; /* IMP_CTRL2 */

			    0x58 0x224 /* IMP_CTRL2 */

			    0x32 0x240 /* TUNE1 */

			    0x29 0x244 /* TUNE2 */

			    0xca 0x248 /* TUNE3 */

			    0x04 0x24c /* TUNE4 */

			    0x00 0x250 /* TUNE5 */

			    0x00 0x23c /* CHG_CTRL2 */

			    0x22 0x210>; /* PWR_CTRL1 */



		phy_type= "utmi";

		clocks = <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
@@ -166,15 +176,25 @@ 
		qcom,vdd-voltage-level = <0 880000 880000>;

		qcom,qusb-phy-init-seq =

			/* <value reg_offset> */

					<0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */

			   <0x23 0x210 /* PWR_CTRL1 */

			   0x03 0x04  /* PLL_ANALOG_CONTROLS_TWO */

			   0x7c 0x18c /* PLL_CLOCK_INVERTERS */

			   0x80 0x2c  /* PLL_CMODE */

			   0x0a 0x184 /* PLL_LOCK_DELAY */

			   0x19 0xb4  /* PLL_DIGITAL_TIMERS_TWO */

					0xa5 0x240 /* TUNE1 */

					0x09 0x244 /* TUNE2 */

			   0x40 0x194 /* PLL_BIAS_CONTROL_1 */

			   0x20 0x198 /* PLL_BIAS_CONTROL_2 */

			   0x21 0x214 /* PWR_CTRL2 */

			   0x00 0x220 /* IMP_CTRL1 */

					0x58 0x224>; /* IMP_CTRL2 */

			   0x58 0x224 /* IMP_CTRL2 */

			   0x32 0x240 /* TUNE1 */

			   0x29 0x244 /* TUNE2 */

			   0xca 0x248 /* TUNE3 */

			   0x04 0x24c /* TUNE4 */

			   0x00 0x250 /* TUNE5 */

			   0x00 0x23c /* CHG_CTRL2 */

			   0x22 0x210>; /* PWR_CTRL1 */



		phy_type= "utmi";

		clocks = <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;