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Commit c8d09530 authored by Vara Reddy's avatar Vara Reddy
Browse files

clk: mdss: adjust PLL disable sequence to avoid glitch 



Adjust the PLL disable sequence as per the latest HW
programming guidelines to ensure there will not be any
stray clock glitches when PLL is turned OFF abruptly.

Change-Id: I3636d09df4e86601e8b5189db1ad088a66f83489
Signed-off-by: default avatarVara Reddy <varar@codeaurora.org>
parent 6d6d60c0

drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c

+11 −3
Original line number Diff line number Diff line
@@ -665,7 +665,6 @@ static int dsi_pll_enable(struct dsi_pll_vco_clk *vco) 


static void dsi_pll_disable_sub(struct mdss_pll_resources *rsc)

{

	dsi_pll_disable_global_clk(rsc);

	MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_RBUF_CTRL, 0);

	dsi_pll_disable_pll_bias(rsc);

}
@@ -684,11 +683,20 @@ static void dsi_pll_disable(struct dsi_pll_vco_clk *vco) 


	pr_debug("stop PLL (%d)\n", rsc->index);



	/*

	 * To avoid any stray glitches while

	 * abruptly powering down the PLL

	 * make sure to gate the clock using

	 * the clock enable bit before powering

	 * down the PLL

	 */

	dsi_pll_disable_global_clk(rsc);

	MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_PLL_CNTRL, 0);

	dsi_pll_disable_sub(rsc);

	if (rsc->slave)

	if (rsc->slave) {

		dsi_pll_disable_global_clk(rsc->slave);

		dsi_pll_disable_sub(rsc->slave);



	}

	/* flush, ensure all register writes are done*/

	wmb();

	rsc->pll_on = false;