Merge branch 'topic/stm32' into for-linus

* STMicroelectronics STM32 DMA controller

The STM32 DMA is a general-purpose direct memory access controller capable of

supporting 8 independent DMA channels. Each channel can have up to 8 requests.

Required properties:

- compatible: Should be "st,stm32-dma"

- reg: Should contain DMA registers location and length. This should include

  all of the per-channel registers.

- interrupts: Should contain all of the per-channel DMA interrupts in

  ascending order with respect to the DMA channel index.

- clocks: Should contain the input clock of the DMA instance.

- #dma-cells : Must be <4>. See DMA client paragraph for more details.

Optional properties:

- resets: Reference to a reset controller asserting the DMA controller

- st,mem2mem: boolean; if defined, it indicates that the controller supports

  memory-to-memory transfer

Example:

	dma2: dma-controller@40026400 {

		compatible = "st,stm32-dma";

		reg = <0x40026400 0x400>;

		interrupts = <56>,

			     <57>,

			     <58>,

			     <59>,

			     <60>,

			     <68>,

			     <69>,

			     <70>;

		clocks = <&clk_hclk>;

		#dma-cells = <4>;

		st,mem2mem;

		resets = <&rcc 150>;

	};

* DMA client

DMA clients connected to the STM32 DMA controller must use the format

described in the dma.txt file, using a five-cell specifier for each

channel: a phandle plus four integer cells.

The four cells in order are:

1. The channel id

2. The request line number

3. A 32bit mask specifying the DMA channel configuration which are device

   dependent:

  -bit 9: Peripheral Increment Address

	0x0: no address increment between transfers

	0x1: increment address between transfers

 -bit 10: Memory Increment Address

	0x0: no address increment between transfers

	0x1: increment address between transfers

 -bit 15: Peripheral Increment Offset Size

	0x0: offset size is linked to the peripheral bus width

	0x1: offset size is fixed to 4 (32-bit alignment)

 -bit 16-17: Priority level

	0x0: low

	0x1: medium

	0x2: high

	0x3: very high

5. A 32bit mask specifying the DMA FIFO threshold configuration which are device

   dependent:

 -bit 0-1: Fifo threshold

	0x0: 1/4 full FIFO

	0x1: 1/2 full FIFO

	0x2: 3/4 full FIFO

	0x3: full FIFO

Example:

	usart1: serial@40011000 {

		compatible = "st,stm32-usart", "st,stm32-uart";

		reg = <0x40011000 0x400>;

		interrupts = <37>;

		clocks = <&clk_pclk2>;

		dmas = <&dma2 2 4 0x10400 0x3>,

		       <&dma2 7 5 0x10200 0x3>;

		dma-names = "rx", "tx";

	};

CONFIG_LEDS_CLASS=y

CONFIG_LEDS_TRIGGERS=y

CONFIG_LEDS_TRIGGER_HEARTBEAT=y

CONFIG_DMADEVICES=y

CONFIG_STM32_DMA=y

# CONFIG_FILE_LOCKING is not set

# CONFIG_DNOTIFY is not set

# CONFIG_INOTIFY_USER is not set

	help

	  Support for ST-Ericsson DMA40 controller

config STM32_DMA

	bool "STMicroelectronics STM32 DMA support"

	depends on ARCH_STM32

	select DMA_ENGINE

	select DMA_OF

	select DMA_VIRTUAL_CHANNELS

	help

	  Enable support for the on-chip DMA controller on STMicroelectronics

	  STM32 MCUs.

	  If you have a board based on such a MCU and wish to use DMA say Y or M

	  here.

config S3C24XX_DMAC

	tristate "Samsung S3C24XX DMA support"

	depends on ARCH_S3C24XX

obj-$(CONFIG_RENESAS_DMA) += sh/

obj-$(CONFIG_SIRF_DMA) += sirf-dma.o

obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o

obj-$(CONFIG_STM32_DMA) += stm32-dma.o

obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o

obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o

obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o