Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c836a412 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: add functions to get current pcie lanes 



Currently unused.

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent c913e23a

drivers/gpu/drm/radeon/r300.c

+31 −0
Original line number Diff line number Diff line
@@ -580,6 +580,37 @@ void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) 


}



int rv370_get_pcie_lanes(struct radeon_device *rdev)

{

	u32 link_width_cntl;



	if (rdev->flags & RADEON_IS_IGP)

		return 0;



	if (!(rdev->flags & RADEON_IS_PCIE))

		return 0;



	/* FIXME wait for idle */



	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);



	switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {

	case RADEON_PCIE_LC_LINK_WIDTH_X0:

		return 0;

	case RADEON_PCIE_LC_LINK_WIDTH_X1:

		return 1;

	case RADEON_PCIE_LC_LINK_WIDTH_X2:

		return 2;

	case RADEON_PCIE_LC_LINK_WIDTH_X4:

		return 4;

	case RADEON_PCIE_LC_LINK_WIDTH_X8:

		return 8;

	case RADEON_PCIE_LC_LINK_WIDTH_X16:

	default:

		return 16;

	}

}



#if defined(CONFIG_DEBUG_FS)

static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)

{

drivers/gpu/drm/radeon/radeon.h

+2 −0
Original line number Diff line number Diff line
@@ -678,6 +678,7 @@ struct radeon_asic { 
	void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);

	uint32_t (*get_memory_clock)(struct radeon_device *rdev);

	void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);

	int (*get_pcie_lanes)(struct radeon_device *rdev);

	void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);

	void (*set_clock_gating)(struct radeon_device *rdev, int enable);

	int (*set_surface_reg)(struct radeon_device *rdev, int reg,
@@ -1044,6 +1045,7 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) 
#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))

#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))

#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))

#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))

#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))

#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))

#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))

drivers/gpu/drm/radeon/radeon_asic.h

+11 −0
Original line number Diff line number Diff line
@@ -108,6 +108,7 @@ static struct radeon_asic r100_asic = { 
	.set_engine_clock = &radeon_legacy_set_engine_clock,

	.get_memory_clock = &radeon_legacy_get_memory_clock,

	.set_memory_clock = NULL,

	.get_pcie_lanes = NULL,

	.set_pcie_lanes = NULL,

	.set_clock_gating = &radeon_legacy_set_clock_gating,

	.set_surface_reg = r100_set_surface_reg,
@@ -138,6 +139,7 @@ extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t 
extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);

extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);

extern int rv370_get_pcie_lanes(struct radeon_device *rdev);

extern int r300_copy_dma(struct radeon_device *rdev,

			uint64_t src_offset,

			uint64_t dst_offset,
@@ -168,6 +170,7 @@ static struct radeon_asic r300_asic = { 
	.set_engine_clock = &radeon_legacy_set_engine_clock,

	.get_memory_clock = &radeon_legacy_get_memory_clock,

	.set_memory_clock = NULL,

	.get_pcie_lanes = &rv370_get_pcie_lanes,

	.set_pcie_lanes = &rv370_set_pcie_lanes,

	.set_clock_gating = &radeon_legacy_set_clock_gating,

	.set_surface_reg = r100_set_surface_reg,
@@ -212,6 +215,7 @@ static struct radeon_asic r420_asic = { 
	.set_engine_clock = &radeon_atom_set_engine_clock,

	.get_memory_clock = &radeon_atom_get_memory_clock,

	.set_memory_clock = &radeon_atom_set_memory_clock,

	.get_pcie_lanes = &rv370_get_pcie_lanes,

	.set_pcie_lanes = &rv370_set_pcie_lanes,

	.set_clock_gating = &radeon_atom_set_clock_gating,

	.set_surface_reg = r100_set_surface_reg,
@@ -261,6 +265,7 @@ static struct radeon_asic rs400_asic = { 
	.set_engine_clock = &radeon_legacy_set_engine_clock,

	.get_memory_clock = &radeon_legacy_get_memory_clock,

	.set_memory_clock = NULL,

	.get_pcie_lanes = NULL,

	.set_pcie_lanes = NULL,

	.set_clock_gating = &radeon_legacy_set_clock_gating,

	.set_surface_reg = r100_set_surface_reg,
@@ -320,6 +325,7 @@ static struct radeon_asic rs600_asic = { 
	.set_engine_clock = &radeon_atom_set_engine_clock,

	.get_memory_clock = &radeon_atom_get_memory_clock,

	.set_memory_clock = &radeon_atom_set_memory_clock,

	.get_pcie_lanes = NULL,

	.set_pcie_lanes = NULL,

	.set_clock_gating = &radeon_atom_set_clock_gating,

	.bandwidth_update = &rs600_bandwidth_update,
@@ -366,6 +372,7 @@ static struct radeon_asic rs690_asic = { 
	.set_engine_clock = &radeon_atom_set_engine_clock,

	.get_memory_clock = &radeon_atom_get_memory_clock,

	.set_memory_clock = &radeon_atom_set_memory_clock,

	.get_pcie_lanes = NULL,

	.set_pcie_lanes = NULL,

	.set_clock_gating = &radeon_atom_set_clock_gating,

	.set_surface_reg = r100_set_surface_reg,
@@ -418,6 +425,7 @@ static struct radeon_asic rv515_asic = { 
	.set_engine_clock = &radeon_atom_set_engine_clock,

	.get_memory_clock = &radeon_atom_get_memory_clock,

	.set_memory_clock = &radeon_atom_set_memory_clock,

	.get_pcie_lanes = &rv370_get_pcie_lanes,

	.set_pcie_lanes = &rv370_set_pcie_lanes,

	.set_clock_gating = &radeon_atom_set_clock_gating,

	.set_surface_reg = r100_set_surface_reg,
@@ -461,6 +469,7 @@ static struct radeon_asic r520_asic = { 
	.set_engine_clock = &radeon_atom_set_engine_clock,

	.get_memory_clock = &radeon_atom_get_memory_clock,

	.set_memory_clock = &radeon_atom_set_memory_clock,

	.get_pcie_lanes = &rv370_get_pcie_lanes,

	.set_pcie_lanes = &rv370_set_pcie_lanes,

	.set_clock_gating = &radeon_atom_set_clock_gating,

	.set_surface_reg = r100_set_surface_reg,
@@ -538,6 +547,7 @@ static struct radeon_asic r600_asic = { 
	.set_engine_clock = &radeon_atom_set_engine_clock,

	.get_memory_clock = &radeon_atom_get_memory_clock,

	.set_memory_clock = &radeon_atom_set_memory_clock,

	.get_pcie_lanes = NULL,

	.set_pcie_lanes = NULL,

	.set_clock_gating = &radeon_atom_set_clock_gating,

	.set_surface_reg = r600_set_surface_reg,
@@ -583,6 +593,7 @@ static struct radeon_asic rv770_asic = { 
	.set_engine_clock = &radeon_atom_set_engine_clock,

	.get_memory_clock = &radeon_atom_get_memory_clock,

	.set_memory_clock = &radeon_atom_set_memory_clock,

	.get_pcie_lanes = NULL,

	.set_pcie_lanes = NULL,

	.set_clock_gating = &radeon_atom_set_clock_gating,

	.set_surface_reg = r600_set_surface_reg,