Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c8354901 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 

* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
  drm/radeon/kms/evergreen: emit SQ_LDS_RESOURCE_MGMT for blits
  agp/intel: Fix typo in G4x_GMCH_SIZE_VT_2M
  drm/radeon/kms: fix typo in read_disabled vbios code
  drm/radeon/kms: use correct BUS_CNTL reg on rs600
  drm/radeon/kms: fix backend map typo on juniper
  drm/radeon/kms: fix regression in hotplug
parents 5d7d5d93 c61d0af9

drivers/char/agp/intel-agp.h

+4 −3
Original line number Diff line number Diff line
@@ -90,9 +90,10 @@ 
#define G4x_GMCH_SIZE_MASK	(0xf << 8)

#define G4x_GMCH_SIZE_1M	(0x1 << 8)

#define G4x_GMCH_SIZE_2M	(0x3 << 8)

#define G4x_GMCH_SIZE_VT_1M	(0x9 << 8)

#define G4x_GMCH_SIZE_VT_1_5M	(0xa << 8)

#define G4x_GMCH_SIZE_VT_2M	(0xc << 8)

#define G4x_GMCH_SIZE_VT_EN	(0x8 << 8)

#define G4x_GMCH_SIZE_VT_1M	(G4x_GMCH_SIZE_1M | G4x_GMCH_SIZE_VT_EN)

#define G4x_GMCH_SIZE_VT_1_5M	((0x2 << 8) | G4x_GMCH_SIZE_VT_EN)

#define G4x_GMCH_SIZE_VT_2M	(G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN)



#define GFX_FLSH_CNTL		0x2170 /* 915+ */

drivers/gpu/drm/radeon/evergreen.c

+1 −1
Original line number Diff line number Diff line
@@ -2000,7 +2000,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
			gb_backend_map = 0x66442200;

			break;

		case CHIP_JUNIPER:

			gb_backend_map = 0x00006420;

			gb_backend_map = 0x00002200;

			break;

		default:

			gb_backend_map =

drivers/gpu/drm/radeon/evergreen_blit_kms.c

+7 −2
Original line number Diff line number Diff line
@@ -252,7 +252,7 @@ draw_auto(struct radeon_device *rdev) 


}



/* emits 36 */

/* emits 39 */

static void

set_default_state(struct radeon_device *rdev)

{
@@ -531,6 +531,11 @@ set_default_state(struct radeon_device *rdev) 
		radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);

		radeon_ring_write(rdev, 0);



		/* setup LDS */

		radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));

		radeon_ring_write(rdev, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2);

		radeon_ring_write(rdev, 0x10001000);



		/* SQ config */

		radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11));

		radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
@@ -773,7 +778,7 @@ int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) 
	/* calculate number of loops correctly */

	ring_size = num_loops * dwords_per_loop;

	/* set default  + shaders */

	ring_size += 52; /* shaders + def state */

	ring_size += 55; /* shaders + def state */

	ring_size += 10; /* fence emit for VB IB */

	ring_size += 5; /* done copy */

	ring_size += 10; /* fence emit for done copy */

drivers/gpu/drm/radeon/radeon_bios.c

+15 −6
Original line number Diff line number Diff line
@@ -331,7 +331,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev) 


	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);

	viph_control = RREG32(RADEON_VIPH_CONTROL);

	bus_cntl = RREG32(RADEON_BUS_CNTL);

	bus_cntl = RREG32(RV370_BUS_CNTL);

	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);

	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);

	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
@@ -350,7 +350,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev) 
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));



	/* enable the rom */

	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));

	WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));



	/* Disable VGA mode */

	WREG32(AVIVO_D1VGA_CONTROL,
@@ -367,7 +367,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev) 
	/* restore regs */

	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);

	WREG32(RADEON_VIPH_CONTROL, viph_control);

	WREG32(RADEON_BUS_CNTL, bus_cntl);

	WREG32(RV370_BUS_CNTL, bus_cntl);

	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);

	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);

	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
@@ -390,6 +390,9 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev) 


	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);

	viph_control = RREG32(RADEON_VIPH_CONTROL);

	if (rdev->flags & RADEON_IS_PCIE)

		bus_cntl = RREG32(RV370_BUS_CNTL);

	else

		bus_cntl = RREG32(RADEON_BUS_CNTL);

	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);

	crtc2_gen_cntl = 0;
@@ -412,6 +415,9 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev) 
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));



	/* enable the rom */

	if (rdev->flags & RADEON_IS_PCIE)

		WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));

	else

		WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));



	/* Turn off mem requests and CRTC for both controllers */
@@ -439,6 +445,9 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev) 
	/* restore regs */

	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);

	WREG32(RADEON_VIPH_CONTROL, viph_control);

	if (rdev->flags & RADEON_IS_PCIE)

		WREG32(RV370_BUS_CNTL, bus_cntl);

	else

		WREG32(RADEON_BUS_CNTL, bus_cntl);

	WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);

	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {

drivers/gpu/drm/radeon/radeon_connectors.c

+6 −0
Original line number Diff line number Diff line
@@ -52,6 +52,12 @@ void radeon_connector_hotplug(struct drm_connector *connector) 
	struct radeon_device *rdev = dev->dev_private;

	struct radeon_connector *radeon_connector = to_radeon_connector(connector);



	/* bail if the connector does not have hpd pin, e.g.,

	 * VGA, TV, etc.

	 */

	if (radeon_connector->hpd.hpd == RADEON_HPD_NONE)

		return;



	radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);



	/* powering up/down the eDP panel generates hpd events which