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Commit c7f1c92a authored by Florian Fainelli's avatar Florian Fainelli Committed by Greg Kroah-Hartman
Browse files

net: dsa: b53: Support setting learning on port 



commit f9b3827ee66cfcf297d0acd6ecf33653a5f297ef upstream.

Add support for being able to set the learning attribute on port, and
make sure that the standalone ports start up with learning disabled.

We can remove the code in bcm_sf2 that configured the ports learning
attribute because we want the standalone ports to have learning disabled
by default and port 7 cannot be bridged, so its learning attribute will
not change past its initial configuration.

Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Reviewed-by: default avatarVladimir Oltean <olteanv@gmail.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 58ef3832

drivers/net/dsa/b53/b53_common.c

+20 −0
Original line number Diff line number Diff line
@@ -502,6 +502,19 @@ static void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 
	}

}



static void b53_port_set_learning(struct b53_device *dev, int port,

				  bool learning)

{

	u16 reg;



	b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, &reg);

	if (learning)

		reg &= ~BIT(port);

	else

		reg |= BIT(port);

	b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg);

}



static int b53_enable_port(struct dsa_switch *ds, int port,

			   struct phy_device *phy)

{
@@ -509,6 +522,8 @@ static int b53_enable_port(struct dsa_switch *ds, int port, 
	unsigned int cpu_port = dev->cpu_port;

	u16 pvlan;



	b53_port_set_learning(dev, port, false);



	/* Clear the Rx and Tx disable bits and set to no spanning tree */

	b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
@@ -552,6 +567,8 @@ static void b53_enable_cpu_port(struct b53_device *dev) 
		    PORT_CTRL_RX_MCST_EN |

		    PORT_CTRL_RX_UCST_EN;

	b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(cpu_port), port_ctrl);



	b53_port_set_learning(dev, cpu_port, false);

}



static void b53_enable_mib(struct b53_device *dev)
@@ -1375,6 +1392,8 @@ static int b53_br_join(struct dsa_switch *ds, int port, 
	b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);

	dev->ports[port].vlan_ctl_mask = pvlan;



	b53_port_set_learning(dev, port, true);



	return 0;

}
@@ -1426,6 +1445,7 @@ static void b53_br_leave(struct dsa_switch *ds, int port) 
		vl->untag |= BIT(port) | BIT(dev->cpu_port);

		b53_set_vlan_entry(dev, pvid, vl);

	}

	b53_port_set_learning(dev, port, false);

}



static void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)

drivers/net/dsa/b53/b53_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -112,6 +112,7 @@ 
#define B53_UC_FLOOD_MASK		0x32

#define B53_MC_FLOOD_MASK		0x34

#define B53_IPMC_FLOOD_MASK		0x36

#define B53_DIS_LEARNING		0x3c



/*

 * Override Ports 0-7 State on devices with xMII interfaces (8 bit)

drivers/net/dsa/bcm_sf2.c

+5 −0
Original line number Diff line number Diff line
@@ -224,6 +224,11 @@ static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 
	reg &= ~P_TXQ_PSM_VDD(port);

	core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);



	/* Disable learning */

	reg = core_readl(priv, CORE_DIS_LEARN);

	reg |= BIT(port);

	core_writel(priv, reg, CORE_DIS_LEARN);



	/* Clear the Rx and Tx disable bits and set to no spanning tree */

	core_writel(priv, 0, CORE_G_PCTL_PORT(port));

drivers/net/dsa/bcm_sf2_regs.h

+2 −0
Original line number Diff line number Diff line
@@ -138,6 +138,8 @@ 
#define CORE_SWITCH_CTRL		0x00088

#define  MII_DUMB_FWDG_EN		(1 << 6)



#define CORE_DIS_LEARN			0x000f0



#define CORE_SFT_LRN_CTRL		0x000f8

#define  SW_LEARN_CNTL(x)		(1 << (x))