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Commit c7db5c56 authored by Gopikrishnaiah Anandan's avatar Gopikrishnaiah Anandan Committed by Gerrit - the friendly Code Review server
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drm/msm/sde: Fix gamma correction table indexing 



Gamma correction table index was incorrectly set which will lead to
color swap issue. Change fixes the index calculation and uses the reg
dma method to set the opcode/swap registers.

Change-Id: Ia0bee41c913108dcb4e70c0dd0701aa0a6bee904
Signed-off-by: default avatarGopikrishnaiah Anandan <agopik@codeaurora.org>
parent cd476038

drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c

+22 −7
Original line number Diff line number Diff line
@@ -529,14 +529,34 @@ void reg_dmav1_setup_dspp_gcv18(struct sde_hw_dspp *ctx, void *cfg) 
		REG_DMA_SETUP_OPS(dma_write_cfg,

			ctx->cap->sblk->gc.base + GC_C0_OFF +

			(i * sizeof(u32) * 2),

			lut_cfg->c0 + ARRAY_SIZE(lut_cfg->c0),

			lut_cfg->c0 + (ARRAY_SIZE(lut_cfg->c0) * i),

			PGC_TBL_LEN * sizeof(u32),

			REG_BLK_WRITE_INC, 0, 0);

		rc = dma_ops->setup_payload(&dma_write_cfg);

		if (rc) {

			DRM_ERROR("index init failed ret %d\n", rc);

			DRM_ERROR("lut write failed ret %d\n", rc);

			return;

		}

	}



	reg = BIT(0);

	REG_DMA_SETUP_OPS(dma_write_cfg,

		ctx->cap->sblk->gc.base + GC_LUT_SWAP_OFF,

		&reg, sizeof(reg), REG_SINGLE_WRITE, 0, 0);

	rc = dma_ops->setup_payload(&dma_write_cfg);

	if (rc) {

		DRM_ERROR("setting swap offset failed ret %d\n", rc);

		return;

	}



	reg = GC_EN | ((lut_cfg->flags & PGC_8B_ROUND) ? GC_8B_ROUND_EN : 0);

	REG_DMA_SETUP_OPS(dma_write_cfg,

		ctx->cap->sblk->gc.base,

		&reg, sizeof(reg), REG_SINGLE_WRITE, 0, 0);

	rc = dma_ops->setup_payload(&dma_write_cfg);

	if (rc) {

		DRM_ERROR("enabling gamma correction failed ret %d\n", rc);

		return;

	}



	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, dspp_buf[GC][ctx->idx],
@@ -547,11 +567,6 @@ void reg_dmav1_setup_dspp_gcv18(struct sde_hw_dspp *ctx, void *cfg) 
		DRM_ERROR("failed to kick off ret %d\n", rc);

		return;

	}



	reg = GC_EN | ((lut_cfg->flags & PGC_8B_ROUND) ? GC_8B_ROUND_EN : 0);

	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->gc.base + GC_LUT_SWAP_OFF,

			BIT(0));

	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->gc.base, reg);

}



int reg_dmav1_deinit_dspp_ops(enum sde_dspp idx)