Loading drivers/video/fbdev/msm/mdss_hdmi_util.c +8 −6 Original line number Diff line number Diff line Loading @@ -1389,6 +1389,7 @@ int hdmi_scdc_read(struct hdmi_tx_ddc_ctrl *ctrl, u32 data_type, u32 *val) rc = hdmi_ddc_read(ctrl); if (rc) { pr_err("DDC Read failed for %s\n", data.what); ctrl->ddc_data.data_buf = NULL; return rc; } Loading Loading @@ -1428,7 +1429,7 @@ int hdmi_scdc_read(struct hdmi_tx_ddc_ctrl *ctrl, u32 data_type, u32 *val) default: break; } ctrl->ddc_data.data_buf = NULL; return 0; } Loading Loading @@ -1469,7 +1470,7 @@ int hdmi_scdc_write(struct hdmi_tx_ddc_ctrl *ctrl, u32 data_type, u32 val) rc = hdmi_ddc_read(ctrl); if (rc) { pr_err("scdc read failed\n"); return rc; goto scdc_write_fail; } if (data_type == HDMI_TX_SCDC_SCRAMBLING_ENABLE) { data_buf[0] = ((((u8)(read_val & 0xFF)) & (~BIT(0))) | Loading @@ -1491,7 +1492,8 @@ int hdmi_scdc_write(struct hdmi_tx_ddc_ctrl *ctrl, u32 data_type, u32 val) default: pr_err("Cannot write to read only reg (%d)\n", data_type); return -EINVAL; rc = -EINVAL; goto scdc_write_fail; } ctrl->ddc_data = data; Loading @@ -1499,10 +1501,10 @@ int hdmi_scdc_write(struct hdmi_tx_ddc_ctrl *ctrl, u32 data_type, u32 val) rc = hdmi_ddc_write(ctrl); if (rc) { pr_err("DDC Read failed for %s\n", data.what); return rc; } return 0; scdc_write_fail: ctrl->ddc_data.data_buf = NULL; return rc; } int hdmi_setup_ddc_timers(struct hdmi_tx_ddc_ctrl *ctrl, Loading drivers/video/fbdev/msm/mdss_mdp_intf_cmd.c +1 −0 Original line number Diff line number Diff line Loading @@ -709,6 +709,7 @@ int mdss_mdp_get_split_display_ctls(struct mdss_mdp_ctl **ctl, swap(*ctl, *sctl); } } else { rc = -EINVAL; pr_debug("%s no split mode:%d\n", __func__, (*ctl)->mfd->split_mode); } Loading Loading
drivers/video/fbdev/msm/mdss_hdmi_util.c +8 −6 Original line number Diff line number Diff line Loading @@ -1389,6 +1389,7 @@ int hdmi_scdc_read(struct hdmi_tx_ddc_ctrl *ctrl, u32 data_type, u32 *val) rc = hdmi_ddc_read(ctrl); if (rc) { pr_err("DDC Read failed for %s\n", data.what); ctrl->ddc_data.data_buf = NULL; return rc; } Loading Loading @@ -1428,7 +1429,7 @@ int hdmi_scdc_read(struct hdmi_tx_ddc_ctrl *ctrl, u32 data_type, u32 *val) default: break; } ctrl->ddc_data.data_buf = NULL; return 0; } Loading Loading @@ -1469,7 +1470,7 @@ int hdmi_scdc_write(struct hdmi_tx_ddc_ctrl *ctrl, u32 data_type, u32 val) rc = hdmi_ddc_read(ctrl); if (rc) { pr_err("scdc read failed\n"); return rc; goto scdc_write_fail; } if (data_type == HDMI_TX_SCDC_SCRAMBLING_ENABLE) { data_buf[0] = ((((u8)(read_val & 0xFF)) & (~BIT(0))) | Loading @@ -1491,7 +1492,8 @@ int hdmi_scdc_write(struct hdmi_tx_ddc_ctrl *ctrl, u32 data_type, u32 val) default: pr_err("Cannot write to read only reg (%d)\n", data_type); return -EINVAL; rc = -EINVAL; goto scdc_write_fail; } ctrl->ddc_data = data; Loading @@ -1499,10 +1501,10 @@ int hdmi_scdc_write(struct hdmi_tx_ddc_ctrl *ctrl, u32 data_type, u32 val) rc = hdmi_ddc_write(ctrl); if (rc) { pr_err("DDC Read failed for %s\n", data.what); return rc; } return 0; scdc_write_fail: ctrl->ddc_data.data_buf = NULL; return rc; } int hdmi_setup_ddc_timers(struct hdmi_tx_ddc_ctrl *ctrl, Loading
drivers/video/fbdev/msm/mdss_mdp_intf_cmd.c +1 −0 Original line number Diff line number Diff line Loading @@ -709,6 +709,7 @@ int mdss_mdp_get_split_display_ctls(struct mdss_mdp_ctl **ctl, swap(*ctl, *sctl); } } else { rc = -EINVAL; pr_debug("%s no split mode:%d\n", __func__, (*ctl)->mfd->split_mode); } Loading