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Commit c7753e90 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-rockchip-next-2016-01-06' of... 

Merge branch 'drm-rockchip-next-2016-01-06' of https://github.com/markyzq/kernel-drm-rockchip into drm-next

new rockchip bits.

* 'drm-rockchip-next-2016-01-06' of https://github.com/markyzq/kernel-drm-rockchip:
  drm: rockchip: Support Synopsys DW MIPI DSI
  Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver
  drm/rockchip: return a true clock rate to adjusted_mode
parents a50e2bf5 84e05408

Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt

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Rockchip specific extensions to the Synopsys Designware MIPI DSI

================================



Required properties:

- #address-cells: Should be <1>.

- #size-cells: Should be <0>.

- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".

- reg: Represent the physical address range of the controller.

- interrupts: Represent the controller's interrupt to the CPU(s).

- clocks, clock-names: Phandles to the controller's pll reference

  clock(ref) and APB clock(pclk), as described in [1].

- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.

- ports: contain a port node with endpoint definitions as defined in [2].

  For vopb,set the reg = <0> and set the reg = <1> for vopl.



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

[2] Documentation/devicetree/bindings/media/video-interfaces.txt



Example:

	mipi_dsi: mipi@ff960000 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";

		reg = <0xff960000 0x4000>;

		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;

		clock-names = "ref", "pclk";

		rockchip,grf = <&grf>;

		status = "okay";



		ports {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <1>;



			mipi_in: port {

				#address-cells = <1>;

				#size-cells = <0>;

				mipi_in_vopb: endpoint@0 {

					reg = <0>;

					remote-endpoint = <&vopb_out_mipi>;

				};

				mipi_in_vopl: endpoint@1 {

					reg = <1>;

					remote-endpoint = <&vopl_out_mipi>;

				};

			};

		};



		panel {

			compatible ="boe,tv080wum-nl0";

			reg = <0>;



			enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;

			pinctrl-names = "default";

			pinctrl-0 = <&lcd_en>;

			backlight = <&backlight>;

			status = "okay";

		};

	};

drivers/gpu/drm/rockchip/Kconfig

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@@ -25,3 +25,13 @@ config ROCKCHIP_DW_HDMI 
	  for the Synopsys DesignWare HDMI driver. If you want to

	  enable HDMI on RK3288 based SoC, you should selet this

	  option.



config ROCKCHIP_DW_MIPI_DSI

	tristate "Rockchip specific extensions for Synopsys DW MIPI DSI"

	depends on DRM_ROCKCHIP

	select DRM_MIPI_DSI

	help

	 This selects support for Rockchip SoC specific extensions

	 for the Synopsys DesignWare HDMI driver. If you want to

	 enable MIPI DSI on RK3288 based SoC, you should selet this

	 option.

drivers/gpu/drm/rockchip/Makefile

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@@ -6,6 +6,7 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \ 
		rockchip_drm_gem.o



obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o

obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o



obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o \

				rockchip_vop_reg.o

drivers/gpu/drm/rockchip/dw-mipi-dsi.c

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File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

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@@ -818,6 +818,9 @@ int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, 
	case DRM_MODE_CONNECTOR_HDMIA:

		VOP_CTRL_SET(vop, hdmi_en, 1);

		break;

	case DRM_MODE_CONNECTOR_DSI:

		VOP_CTRL_SET(vop, mipi_en, 1);

		break;

	default:

		DRM_ERROR("unsupport connector_type[%d]\n", connector_type);

		return -EINVAL;
@@ -878,9 +881,14 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 
				const struct drm_display_mode *mode,

				struct drm_display_mode *adjusted_mode)

{

	struct vop *vop = to_vop(crtc);



	if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)

		return false;



	adjusted_mode->clock =

		clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;



	return true;

}