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Vote for PM QOS by specifying the acceptable CPU to DMA latency so that system can enter into the possible power states without affecting the SDHC performance. Change-Id: I5fcf9aa93da690c6e64ab70ea5b039ca663c80ad Signed-off-by:Sahitya Tummala <stummala@codeaurora.org> Signed-off-by:
Subhash Jadavani <subhashj@codeaurora.org> [xiaonian@codeaurora.org: fix trivial merge conflict] Signed-off-by:
Xiaonian Wang <xiaonian@codeaurora.org>