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Commit c640e8ca authored by Dave Airlie's avatar Dave Airlie
Browse files

drm/radeon: fix page flipping hangs on r300/r400 

We've been getting reports of complete system lockups with rv3xx hw on
AGP and PCIE when running gnome-shell or kwin with compositing.

It appears the hw really doesn't like setting these registers while
stuff is running, this moves the setting of the registers into the modeset
since they aren't required to be changed anywhere else.

fixes: https://bugs.freedesktop.org/show_bug.cgi?id=35183



Reported-and-tested-by: default avatarÁlmos <aaalmosss@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent fdc315a1

drivers/gpu/drm/radeon/r100.c

+0 −17
Original line number Diff line number Diff line
@@ -70,23 +70,6 @@ MODULE_FIRMWARE(FIRMWARE_R520); 


void r100_pre_page_flip(struct radeon_device *rdev, int crtc)

{

	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];

	u32 tmp;



	/* make sure flip is at vb rather than hb */

	tmp = RREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset);

	tmp &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;

	/* make sure pending bit is asserted */

	tmp |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;

	WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, tmp);



	/* set pageflip to happen as late as possible in the vblank interval.

	 * same field for crtc1/2

	 */

	tmp = RREG32(RADEON_CRTC_GEN_CNTL);

	tmp &= ~RADEON_CRTC_VSTAT_MODE_MASK;

	WREG32(RADEON_CRTC_GEN_CNTL, tmp);



	/* enable the pflip int */

	radeon_irq_kms_pflip_irq_get(rdev, crtc);

}

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

+2 −1
Original line number Diff line number Diff line
@@ -443,7 +443,7 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc, 
		       (target_fb->bits_per_pixel * 8));

	crtc_pitch |= crtc_pitch << 16;





	crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;

	if (tiling_flags & RADEON_TILING_MACRO) {

		if (ASIC_IS_R300(rdev))

			crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
@@ -502,6 +502,7 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc, 
	gen_cntl_val = RREG32(gen_cntl_reg);

	gen_cntl_val &= ~(0xf << 8);

	gen_cntl_val |= (format << 8);

	gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK;

	WREG32(gen_cntl_reg, gen_cntl_val);



	crtc_offset = (u32)base;