Loading arch/arm64/boot/dts/qcom/sdm670-pinctrl.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -19,6 +19,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&pdc>; /* QUPv3 South SE mappings */ /* SE 0 pin mappings */ Loading arch/arm64/boot/dts/qcom/sdm670-pm.dtsi +8 −0 Original line number Diff line number Diff line Loading @@ -195,4 +195,12 @@ reg = <0xc300000 0x1000>, <0xc3f0004 0x4>; reg-names = "phys_addr_base", "offset_addr"; }; pdc: interrupt-controller@b220000{ compatible = "qcom,pdc-sdm670"; reg = <0xb220000 0x400>; #interrupt-cells = <3>; interrupt-parent = <&intc>; interrupt-controller; }; }; arch/arm64/boot/dts/qcom/sdm670-qupv3.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -42,7 +42,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se6_4uart_active>; pinctrl-1 = <&qupv3_se6_4uart_sleep>; interrupts-extended = <&intc GIC_SPI 607 0>, interrupts-extended = <&pdc GIC_SPI 607 0>, <&tlmm 48 0>; status = "disabled"; qcom,wakeup-byte = <0xFD>; Loading @@ -60,7 +60,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se7_4uart_active>; pinctrl-1 = <&qupv3_se7_4uart_sleep>; interrupts-extended = <&intc GIC_SPI 608 0>, interrupts-extended = <&pdc GIC_SPI 608 0>, <&tlmm 96 0>; status = "disabled"; qcom,wakeup-byte = <0xFD>; Loading arch/arm64/boot/dts/qcom/sdm670.dtsi +2 −1 Original line number Diff line number Diff line Loading @@ -26,7 +26,7 @@ model = "Qualcomm Technologies, Inc. SDM670"; compatible = "qcom,sdm670"; qcom,msm-id = <336 0x0>; interrupt-parent = <&intc>; interrupt-parent = <&pdc>; aliases { ufshc1 = &ufshc_mem; /* Embedded UFS slot */ Loading Loading @@ -416,6 +416,7 @@ reg = <0x17a00000 0x10000>, /* GICD */ <0x17a60000 0x100000>; /* GICR * 8 */ interrupts = <1 9 4>; interrupt-parent = <&intc>; }; timer { Loading Loading
arch/arm64/boot/dts/qcom/sdm670-pinctrl.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -19,6 +19,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&pdc>; /* QUPv3 South SE mappings */ /* SE 0 pin mappings */ Loading
arch/arm64/boot/dts/qcom/sdm670-pm.dtsi +8 −0 Original line number Diff line number Diff line Loading @@ -195,4 +195,12 @@ reg = <0xc300000 0x1000>, <0xc3f0004 0x4>; reg-names = "phys_addr_base", "offset_addr"; }; pdc: interrupt-controller@b220000{ compatible = "qcom,pdc-sdm670"; reg = <0xb220000 0x400>; #interrupt-cells = <3>; interrupt-parent = <&intc>; interrupt-controller; }; };
arch/arm64/boot/dts/qcom/sdm670-qupv3.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -42,7 +42,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se6_4uart_active>; pinctrl-1 = <&qupv3_se6_4uart_sleep>; interrupts-extended = <&intc GIC_SPI 607 0>, interrupts-extended = <&pdc GIC_SPI 607 0>, <&tlmm 48 0>; status = "disabled"; qcom,wakeup-byte = <0xFD>; Loading @@ -60,7 +60,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se7_4uart_active>; pinctrl-1 = <&qupv3_se7_4uart_sleep>; interrupts-extended = <&intc GIC_SPI 608 0>, interrupts-extended = <&pdc GIC_SPI 608 0>, <&tlmm 96 0>; status = "disabled"; qcom,wakeup-byte = <0xFD>; Loading
arch/arm64/boot/dts/qcom/sdm670.dtsi +2 −1 Original line number Diff line number Diff line Loading @@ -26,7 +26,7 @@ model = "Qualcomm Technologies, Inc. SDM670"; compatible = "qcom,sdm670"; qcom,msm-id = <336 0x0>; interrupt-parent = <&intc>; interrupt-parent = <&pdc>; aliases { ufshc1 = &ufshc_mem; /* Embedded UFS slot */ Loading Loading @@ -416,6 +416,7 @@ reg = <0x17a00000 0x10000>, /* GICD */ <0x17a60000 0x100000>; /* GICR * 8 */ interrupts = <1 9 4>; interrupt-parent = <&intc>; }; timer { Loading