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Commit c5b36783 authored by Steven J. Hill's avatar Steven J. Hill Committed by Ralf Baechle
Browse files

MIPS: Add support for XPA. 



Add support for extended physical addressing (XPA) so that
32-bit platforms can access equal to or greater than 40 bits
of physical addresses.

NOTE:
      1) XPA and EVA are not the same and cannot be used
         simultaneously.
      2) If you configure your kernel for XPA, the PTEs
         and all address sizes become 64-bit.
      3) Your platform MUST have working HIGHMEM support.

Signed-off-by: default avatarSteven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9355/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent be0c37c9

arch/mips/Kconfig

+35 −0
Original line number Diff line number Diff line
@@ -377,6 +377,7 @@ config MIPS_MALTA 
	select SYS_HAS_CPU_MIPS32_R1

	select SYS_HAS_CPU_MIPS32_R2

	select SYS_HAS_CPU_MIPS32_R3_5

	select SYS_HAS_CPU_MIPS32_R5

	select SYS_HAS_CPU_MIPS32_R6

	select SYS_HAS_CPU_MIPS64_R1

	select SYS_HAS_CPU_MIPS64_R2
@@ -386,6 +387,7 @@ config MIPS_MALTA 
	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_HIGHMEM

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_SUPPORTS_MICROMIPS

	select SYS_SUPPORTS_MIPS_CMP
@@ -1596,6 +1598,33 @@ config CPU_MIPS32_3_5_EVA 
	  One of its primary benefits is an increase in the maximum size

	  of lowmem (up to 3GB). If unsure, say 'N' here.



config CPU_MIPS32_R5_FEATURES

	bool "MIPS32 Release 5 Features"

	depends on SYS_HAS_CPU_MIPS32_R5

	depends on CPU_MIPS32_R2

	help

	  Choose this option to build a kernel for release 2 or later of the

	  MIPS32 architecture including features from release 5 such as

	  support for Extended Physical Addressing (XPA).



config CPU_MIPS32_R5_XPA

	bool "Extended Physical Addressing (XPA)"

	depends on CPU_MIPS32_R5_FEATURES

	depends on !EVA

	depends on !PAGE_SIZE_4KB

	depends on SYS_SUPPORTS_HIGHMEM

	select XPA

	select HIGHMEM

	select ARCH_PHYS_ADDR_T_64BIT

	default n

	help

	  Choose this option if you want to enable the Extended Physical

	  Addressing (XPA) on your MIPS32 core (such as P5600 series). The

	  benefit is to increase physical addressing equal to or greater

	  than 40 bits. Note that this has the side effect of turning on

	  64-bit addressing which in turn makes the PTEs 64-bit in size.

	  If unsure, say 'N' here.



if CPU_LOONGSON2F

config CPU_NOP_WORKAROUNDS

	bool
@@ -1699,6 +1728,9 @@ config SYS_HAS_CPU_MIPS32_R2 
config SYS_HAS_CPU_MIPS32_R3_5

	bool



config SYS_HAS_CPU_MIPS32_R5

	bool



config SYS_HAS_CPU_MIPS32_R6

	bool
@@ -1836,6 +1868,9 @@ config CPU_MIPSR6 
config EVA

	bool



config XPA

	bool



config SYS_SUPPORTS_32BIT_KERNEL

	bool

config SYS_SUPPORTS_64BIT_KERNEL

arch/mips/include/asm/cpu-features.h

+3 −0
Original line number Diff line number Diff line
@@ -139,6 +139,9 @@ 
# endif

#endif



#ifndef cpu_has_xpa

#define cpu_has_xpa		(cpu_data[0].options & MIPS_CPU_XPA)

#endif

#ifndef cpu_has_vtag_icache

#define cpu_has_vtag_icache	(cpu_data[0].icache.flags & MIPS_CACHE_VTAG)

#endif

arch/mips/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -377,6 +377,7 @@ enum cpu_type_enum { 
#define MIPS_CPU_MAAR		0x400000000ull /* MAAR(I) registers are present */

#define MIPS_CPU_FRE		0x800000000ull /* FRE & UFE bits implemented */

#define MIPS_CPU_RW_LLB		0x1000000000ull /* LLADDR/LLB writes are allowed */

#define MIPS_CPU_XPA		0x2000000000ull /* CPU supports Extended Physical Addressing */



/*

 * CPU ASE encodings

arch/mips/include/asm/pgtable-32.h

+9 −6
Original line number Diff line number Diff line
@@ -105,13 +105,16 @@ static inline void pmd_clear(pmd_t *pmdp) 


#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)

#define pte_page(x)		pfn_to_page(pte_pfn(x))

#define pte_pfn(x)		((unsigned long)((x).pte_high >> 6))

#define pte_pfn(x)		(((unsigned long)((x).pte_high >> _PFN_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT))

static inline pte_t

pfn_pte(unsigned long pfn, pgprot_t prot)

{

	pte_t pte;

	pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);

	pte.pte_low = pgprot_val(prot);



	pte.pte_low = (pfn >> _PAGE_PRESENT_SHIFT) |

				(pgprot_val(prot) & ~_PFNX_MASK);

	pte.pte_high = (pfn << _PFN_SHIFT) |

				(pgprot_val(prot) & ~_PFN_MASK);

	return pte;

}
@@ -166,9 +169,9 @@ pfn_pte(unsigned long pfn, pgprot_t prot) 
#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)



/* Swap entries must have VALID and GLOBAL bits cleared. */

#define __swp_type(x)			(((x).val >> 2) & 0x1f)

#define __swp_offset(x)			 ((x).val >> 7)

#define __swp_entry(type,offset)	((swp_entry_t)	{ ((type) << 2) | ((offset) << 7) })

#define __swp_type(x)			(((x).val >> 4) & 0x1f)

#define __swp_offset(x)			 ((x).val >> 9)

#define __swp_entry(type,offset)	((swp_entry_t)  { ((type) << 4) | ((offset) << 9) })

#define __pte_to_swp_entry(pte)		((swp_entry_t) { (pte).pte_high })

#define __swp_entry_to_pte(x)		((pte_t) { 0, (x).val })

arch/mips/include/asm/pgtable-bits.h

+11 −2
Original line number Diff line number Diff line
@@ -37,7 +37,11 @@ 
/*

 * The following bits are implemented by the TLB hardware

 */

#define _PAGE_GLOBAL_SHIFT	0

#define _PAGE_NO_EXEC_SHIFT	0

#define _PAGE_NO_EXEC		(1 << _PAGE_NO_EXEC_SHIFT)

#define _PAGE_NO_READ_SHIFT	(_PAGE_NO_EXEC_SHIFT + 1)

#define _PAGE_NO_READ		(1 << _PAGE_NO_READ_SHIFT)

#define _PAGE_GLOBAL_SHIFT	(_PAGE_NO_READ_SHIFT + 1)

#define _PAGE_GLOBAL		(1 << _PAGE_GLOBAL_SHIFT)

#define _PAGE_VALID_SHIFT	(_PAGE_GLOBAL_SHIFT + 1)

#define _PAGE_VALID		(1 << _PAGE_VALID_SHIFT)
@@ -49,7 +53,7 @@ 
/*

 * The following bits are implemented in software

 */

#define _PAGE_PRESENT_SHIFT	(_CACHE_SHIFT + 3)

#define _PAGE_PRESENT_SHIFT	(24)

#define _PAGE_PRESENT		(1 << _PAGE_PRESENT_SHIFT)

#define _PAGE_READ_SHIFT	(_PAGE_PRESENT_SHIFT + 1)

#define _PAGE_READ		(1 << _PAGE_READ_SHIFT)
@@ -62,6 +66,11 @@ 


#define _PFN_SHIFT		(PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)



/*

 * Bits for extended EntryLo0/EntryLo1 registers

 */

#define _PFNX_MASK		0xffffff



#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)



/*