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Commit c5aa59e8 authored by David Daney's avatar David Daney
Browse files

MIPS: OCTEON: Update register definitions. 



Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX.

Add little-endian register layouts.

Patch cvmx-interrupt-rsl.c for changed definition.

Signed-off-by: default avatarDavid Daney <david.daney@cavium.com>
parent 5cf02e55

arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c

+1 −1
Original line number Diff line number Diff line
@@ -130,7 +130,7 @@ void __cvmx_interrupt_gmxx_enable(int interface) 
	if (num_ports) {

		if (OCTEON_IS_MODEL(OCTEON_CN38XX)

		    || OCTEON_IS_MODEL(OCTEON_CN58XX))

			gmx_tx_int_en.s.ncb_nxa = 1;

			gmx_tx_int_en.cn38xx.ncb_nxa = 1;

		gmx_tx_int_en.s.pko_nxa = 1;

	}

	gmx_tx_int_en.s.undflw = (1 << num_ports) - 1;

arch/mips/include/asm/octeon/cvmx-agl-defs.h

+1013 −1

File changed.

Preview size limit exceeded, changes collapsed.

arch/mips/include/asm/octeon/cvmx-asxx-defs.h

+247 −53
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 
 * Contact: support@caviumnetworks.com

 * This file is part of the OCTEON SDK

 *

 * Copyright (c) 2003-2008 Cavium Networks

 * Copyright (c) 2003-2012 Cavium Networks

 *

 * This file is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,64 +28,43 @@ 
#ifndef __CVMX_ASXX_DEFS_H__

#define __CVMX_ASXX_DEFS_H__



#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000180ull + (((block_id) & 0) * 0x8000000ull))

#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000188ull + (((block_id) & 0) * 0x8000000ull))

#define CVMX_ASXX_INT_EN(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000018ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_INT_REG(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000010ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_MII_RX_DAT_SET(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000190ull + (((block_id) & 0) * 0x8000000ull))

#define CVMX_ASXX_PRT_LOOP(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000040ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_RLD_BYPASS(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000248ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000250ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_RLD_COMP(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000220ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_RLD_DATA_DRV(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000218ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000210ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000230ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000240ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000228ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000238ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_RLD_SETTING(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000258ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000020ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_RX_PRT_EN(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000000ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_RX_WOL(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000100ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_RX_WOL_MSK(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000108ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_RX_WOL_POWOK(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000118ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_RX_WOL_SIG(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000110ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000048ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_TX_COMP_BYP(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000068ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000080ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_TX_PRT_EN(block_id) \

	 CVMX_ADD_IO_SEG(0x00011800B0000008ull + (((block_id) & 1) * 0x8000000ull))

#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull))

#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull))

#define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull)

#define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull)

#define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull))

#define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull)

#define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull)

#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull)

#define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull)

#define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull)

#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull)

#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull)

#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull)

#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull)

#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull)

#define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull)

#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)

#define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull)

#define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull)

#define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull)

#define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull)

#define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull)

#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)

#define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull)

#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)

#define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull)



union cvmx_asxx_gmii_rx_clk_set {

	uint64_t u64;

	struct cvmx_asxx_gmii_rx_clk_set_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_5_63:59;

		uint64_t setting:5;

#else

		uint64_t setting:5;

		uint64_t reserved_5_63:59;

#endif

	} s;

	struct cvmx_asxx_gmii_rx_clk_set_s cn30xx;

	struct cvmx_asxx_gmii_rx_clk_set_s cn31xx;
@@ -95,8 +74,13 @@ union cvmx_asxx_gmii_rx_clk_set { 
union cvmx_asxx_gmii_rx_dat_set {

	uint64_t u64;

	struct cvmx_asxx_gmii_rx_dat_set_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_5_63:59;

		uint64_t setting:5;

#else

		uint64_t setting:5;

		uint64_t reserved_5_63:59;

#endif

	} s;

	struct cvmx_asxx_gmii_rx_dat_set_s cn30xx;

	struct cvmx_asxx_gmii_rx_dat_set_s cn31xx;
@@ -106,18 +90,34 @@ union cvmx_asxx_gmii_rx_dat_set { 
union cvmx_asxx_int_en {

	uint64_t u64;

	struct cvmx_asxx_int_en_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_12_63:52;

		uint64_t txpsh:4;

		uint64_t txpop:4;

		uint64_t ovrflw:4;

#else

		uint64_t ovrflw:4;

		uint64_t txpop:4;

		uint64_t txpsh:4;

		uint64_t reserved_12_63:52;

#endif

	} s;

	struct cvmx_asxx_int_en_cn30xx {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_11_63:53;

		uint64_t txpsh:3;

		uint64_t reserved_7_7:1;

		uint64_t txpop:3;

		uint64_t reserved_3_3:1;

		uint64_t ovrflw:3;

#else

		uint64_t ovrflw:3;

		uint64_t reserved_3_3:1;

		uint64_t txpop:3;

		uint64_t reserved_7_7:1;

		uint64_t txpsh:3;

		uint64_t reserved_11_63:53;

#endif

	} cn30xx;

	struct cvmx_asxx_int_en_cn30xx cn31xx;

	struct cvmx_asxx_int_en_s cn38xx;
@@ -130,18 +130,34 @@ union cvmx_asxx_int_en { 
union cvmx_asxx_int_reg {

	uint64_t u64;

	struct cvmx_asxx_int_reg_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_12_63:52;

		uint64_t txpsh:4;

		uint64_t txpop:4;

		uint64_t ovrflw:4;

#else

		uint64_t ovrflw:4;

		uint64_t txpop:4;

		uint64_t txpsh:4;

		uint64_t reserved_12_63:52;

#endif

	} s;

	struct cvmx_asxx_int_reg_cn30xx {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_11_63:53;

		uint64_t txpsh:3;

		uint64_t reserved_7_7:1;

		uint64_t txpop:3;

		uint64_t reserved_3_3:1;

		uint64_t ovrflw:3;

#else

		uint64_t ovrflw:3;

		uint64_t reserved_3_3:1;

		uint64_t txpop:3;

		uint64_t reserved_7_7:1;

		uint64_t txpsh:3;

		uint64_t reserved_11_63:53;

#endif

	} cn30xx;

	struct cvmx_asxx_int_reg_cn30xx cn31xx;

	struct cvmx_asxx_int_reg_s cn38xx;
@@ -154,8 +170,13 @@ union cvmx_asxx_int_reg { 
union cvmx_asxx_mii_rx_dat_set {

	uint64_t u64;

	struct cvmx_asxx_mii_rx_dat_set_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_5_63:59;

		uint64_t setting:5;

#else

		uint64_t setting:5;

		uint64_t reserved_5_63:59;

#endif

	} s;

	struct cvmx_asxx_mii_rx_dat_set_s cn30xx;

	struct cvmx_asxx_mii_rx_dat_set_s cn50xx;
@@ -164,15 +185,28 @@ union cvmx_asxx_mii_rx_dat_set { 
union cvmx_asxx_prt_loop {

	uint64_t u64;

	struct cvmx_asxx_prt_loop_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_8_63:56;

		uint64_t ext_loop:4;

		uint64_t int_loop:4;

#else

		uint64_t int_loop:4;

		uint64_t ext_loop:4;

		uint64_t reserved_8_63:56;

#endif

	} s;

	struct cvmx_asxx_prt_loop_cn30xx {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_7_63:57;

		uint64_t ext_loop:3;

		uint64_t reserved_3_3:1;

		uint64_t int_loop:3;

#else

		uint64_t int_loop:3;

		uint64_t reserved_3_3:1;

		uint64_t ext_loop:3;

		uint64_t reserved_7_63:57;

#endif

	} cn30xx;

	struct cvmx_asxx_prt_loop_cn30xx cn31xx;

	struct cvmx_asxx_prt_loop_s cn38xx;
@@ -185,8 +219,13 @@ union cvmx_asxx_prt_loop { 
union cvmx_asxx_rld_bypass {

	uint64_t u64;

	struct cvmx_asxx_rld_bypass_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_1_63:63;

		uint64_t bypass:1;

#else

		uint64_t bypass:1;

		uint64_t reserved_1_63:63;

#endif

	} s;

	struct cvmx_asxx_rld_bypass_s cn38xx;

	struct cvmx_asxx_rld_bypass_s cn38xxp2;
@@ -197,8 +236,13 @@ union cvmx_asxx_rld_bypass { 
union cvmx_asxx_rld_bypass_setting {

	uint64_t u64;

	struct cvmx_asxx_rld_bypass_setting_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_5_63:59;

		uint64_t setting:5;

#else

		uint64_t setting:5;

		uint64_t reserved_5_63:59;

#endif

	} s;

	struct cvmx_asxx_rld_bypass_setting_s cn38xx;

	struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
@@ -209,14 +253,26 @@ union cvmx_asxx_rld_bypass_setting { 
union cvmx_asxx_rld_comp {

	uint64_t u64;

	struct cvmx_asxx_rld_comp_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_9_63:55;

		uint64_t pctl:5;

		uint64_t nctl:4;

#else

		uint64_t nctl:4;

		uint64_t pctl:5;

		uint64_t reserved_9_63:55;

#endif

	} s;

	struct cvmx_asxx_rld_comp_cn38xx {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_8_63:56;

		uint64_t pctl:4;

		uint64_t nctl:4;

#else

		uint64_t nctl:4;

		uint64_t pctl:4;

		uint64_t reserved_8_63:56;

#endif

	} cn38xx;

	struct cvmx_asxx_rld_comp_cn38xx cn38xxp2;

	struct cvmx_asxx_rld_comp_s cn58xx;
@@ -226,9 +282,15 @@ union cvmx_asxx_rld_comp { 
union cvmx_asxx_rld_data_drv {

	uint64_t u64;

	struct cvmx_asxx_rld_data_drv_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_8_63:56;

		uint64_t pctl:4;

		uint64_t nctl:4;

#else

		uint64_t nctl:4;

		uint64_t pctl:4;

		uint64_t reserved_8_63:56;

#endif

	} s;

	struct cvmx_asxx_rld_data_drv_s cn38xx;

	struct cvmx_asxx_rld_data_drv_s cn38xxp2;
@@ -239,8 +301,13 @@ union cvmx_asxx_rld_data_drv { 
union cvmx_asxx_rld_fcram_mode {

	uint64_t u64;

	struct cvmx_asxx_rld_fcram_mode_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_1_63:63;

		uint64_t mode:1;

#else

		uint64_t mode:1;

		uint64_t reserved_1_63:63;

#endif

	} s;

	struct cvmx_asxx_rld_fcram_mode_s cn38xx;

	struct cvmx_asxx_rld_fcram_mode_s cn38xxp2;
@@ -249,8 +316,13 @@ union cvmx_asxx_rld_fcram_mode { 
union cvmx_asxx_rld_nctl_strong {

	uint64_t u64;

	struct cvmx_asxx_rld_nctl_strong_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_5_63:59;

		uint64_t nctl:5;

#else

		uint64_t nctl:5;

		uint64_t reserved_5_63:59;

#endif

	} s;

	struct cvmx_asxx_rld_nctl_strong_s cn38xx;

	struct cvmx_asxx_rld_nctl_strong_s cn38xxp2;
@@ -261,8 +333,13 @@ union cvmx_asxx_rld_nctl_strong { 
union cvmx_asxx_rld_nctl_weak {

	uint64_t u64;

	struct cvmx_asxx_rld_nctl_weak_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_5_63:59;

		uint64_t nctl:5;

#else

		uint64_t nctl:5;

		uint64_t reserved_5_63:59;

#endif

	} s;

	struct cvmx_asxx_rld_nctl_weak_s cn38xx;

	struct cvmx_asxx_rld_nctl_weak_s cn38xxp2;
@@ -273,8 +350,13 @@ union cvmx_asxx_rld_nctl_weak { 
union cvmx_asxx_rld_pctl_strong {

	uint64_t u64;

	struct cvmx_asxx_rld_pctl_strong_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_5_63:59;

		uint64_t pctl:5;

#else

		uint64_t pctl:5;

		uint64_t reserved_5_63:59;

#endif

	} s;

	struct cvmx_asxx_rld_pctl_strong_s cn38xx;

	struct cvmx_asxx_rld_pctl_strong_s cn38xxp2;
@@ -285,8 +367,13 @@ union cvmx_asxx_rld_pctl_strong { 
union cvmx_asxx_rld_pctl_weak {

	uint64_t u64;

	struct cvmx_asxx_rld_pctl_weak_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_5_63:59;

		uint64_t pctl:5;

#else

		uint64_t pctl:5;

		uint64_t reserved_5_63:59;

#endif

	} s;

	struct cvmx_asxx_rld_pctl_weak_s cn38xx;

	struct cvmx_asxx_rld_pctl_weak_s cn38xxp2;
@@ -297,16 +384,30 @@ union cvmx_asxx_rld_pctl_weak { 
union cvmx_asxx_rld_setting {

	uint64_t u64;

	struct cvmx_asxx_rld_setting_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_13_63:51;

		uint64_t dfaset:5;

		uint64_t dfalag:1;

		uint64_t dfalead:1;

		uint64_t dfalock:1;

		uint64_t setting:5;

#else

		uint64_t setting:5;

		uint64_t dfalock:1;

		uint64_t dfalead:1;

		uint64_t dfalag:1;

		uint64_t dfaset:5;

		uint64_t reserved_13_63:51;

#endif

	} s;

	struct cvmx_asxx_rld_setting_cn38xx {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_5_63:59;

		uint64_t setting:5;

#else

		uint64_t setting:5;

		uint64_t reserved_5_63:59;

#endif

	} cn38xx;

	struct cvmx_asxx_rld_setting_cn38xx cn38xxp2;

	struct cvmx_asxx_rld_setting_s cn58xx;
@@ -316,8 +417,13 @@ union cvmx_asxx_rld_setting { 
union cvmx_asxx_rx_clk_setx {

	uint64_t u64;

	struct cvmx_asxx_rx_clk_setx_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_5_63:59;

		uint64_t setting:5;

#else

		uint64_t setting:5;

		uint64_t reserved_5_63:59;

#endif

	} s;

	struct cvmx_asxx_rx_clk_setx_s cn30xx;

	struct cvmx_asxx_rx_clk_setx_s cn31xx;
@@ -331,12 +437,22 @@ union cvmx_asxx_rx_clk_setx { 
union cvmx_asxx_rx_prt_en {

	uint64_t u64;

	struct cvmx_asxx_rx_prt_en_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_4_63:60;

		uint64_t prt_en:4;

#else

		uint64_t prt_en:4;

		uint64_t reserved_4_63:60;

#endif

	} s;

	struct cvmx_asxx_rx_prt_en_cn30xx {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_3_63:61;

		uint64_t prt_en:3;

#else

		uint64_t prt_en:3;

		uint64_t reserved_3_63:61;

#endif

	} cn30xx;

	struct cvmx_asxx_rx_prt_en_cn30xx cn31xx;

	struct cvmx_asxx_rx_prt_en_s cn38xx;
@@ -349,9 +465,15 @@ union cvmx_asxx_rx_prt_en { 
union cvmx_asxx_rx_wol {

	uint64_t u64;

	struct cvmx_asxx_rx_wol_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_2_63:62;

		uint64_t status:1;

		uint64_t enable:1;

#else

		uint64_t enable:1;

		uint64_t status:1;

		uint64_t reserved_2_63:62;

#endif

	} s;

	struct cvmx_asxx_rx_wol_s cn38xx;

	struct cvmx_asxx_rx_wol_s cn38xxp2;
@@ -360,7 +482,11 @@ union cvmx_asxx_rx_wol { 
union cvmx_asxx_rx_wol_msk {

	uint64_t u64;

	struct cvmx_asxx_rx_wol_msk_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t msk:64;

#else

		uint64_t msk:64;

#endif

	} s;

	struct cvmx_asxx_rx_wol_msk_s cn38xx;

	struct cvmx_asxx_rx_wol_msk_s cn38xxp2;
@@ -369,8 +495,13 @@ union cvmx_asxx_rx_wol_msk { 
union cvmx_asxx_rx_wol_powok {

	uint64_t u64;

	struct cvmx_asxx_rx_wol_powok_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_1_63:63;

		uint64_t powerok:1;

#else

		uint64_t powerok:1;

		uint64_t reserved_1_63:63;

#endif

	} s;

	struct cvmx_asxx_rx_wol_powok_s cn38xx;

	struct cvmx_asxx_rx_wol_powok_s cn38xxp2;
@@ -379,8 +510,13 @@ union cvmx_asxx_rx_wol_powok { 
union cvmx_asxx_rx_wol_sig {

	uint64_t u64;

	struct cvmx_asxx_rx_wol_sig_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_32_63:32;

		uint64_t sig:32;

#else

		uint64_t sig:32;

		uint64_t reserved_32_63:32;

#endif

	} s;

	struct cvmx_asxx_rx_wol_sig_s cn38xx;

	struct cvmx_asxx_rx_wol_sig_s cn38xxp2;
@@ -389,8 +525,13 @@ union cvmx_asxx_rx_wol_sig { 
union cvmx_asxx_tx_clk_setx {

	uint64_t u64;

	struct cvmx_asxx_tx_clk_setx_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_5_63:59;

		uint64_t setting:5;

#else

		uint64_t setting:5;

		uint64_t reserved_5_63:59;

#endif

	} s;

	struct cvmx_asxx_tx_clk_setx_s cn30xx;

	struct cvmx_asxx_tx_clk_setx_s cn31xx;
@@ -404,34 +545,67 @@ union cvmx_asxx_tx_clk_setx { 
union cvmx_asxx_tx_comp_byp {

	uint64_t u64;

	struct cvmx_asxx_tx_comp_byp_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_0_63:64;

#else

		uint64_t reserved_0_63:64;

#endif

	} s;

	struct cvmx_asxx_tx_comp_byp_cn30xx {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_9_63:55;

		uint64_t bypass:1;

		uint64_t pctl:4;

		uint64_t nctl:4;

#else

		uint64_t nctl:4;

		uint64_t pctl:4;

		uint64_t bypass:1;

		uint64_t reserved_9_63:55;

#endif

	} cn30xx;

	struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx;

	struct cvmx_asxx_tx_comp_byp_cn38xx {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_8_63:56;

		uint64_t pctl:4;

		uint64_t nctl:4;

#else

		uint64_t nctl:4;

		uint64_t pctl:4;

		uint64_t reserved_8_63:56;

#endif

	} cn38xx;

	struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2;

	struct cvmx_asxx_tx_comp_byp_cn50xx {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_17_63:47;

		uint64_t bypass:1;

		uint64_t reserved_13_15:3;

		uint64_t pctl:5;

		uint64_t reserved_5_7:3;

		uint64_t nctl:5;

#else

		uint64_t nctl:5;

		uint64_t reserved_5_7:3;

		uint64_t pctl:5;

		uint64_t reserved_13_15:3;

		uint64_t bypass:1;

		uint64_t reserved_17_63:47;

#endif

	} cn50xx;

	struct cvmx_asxx_tx_comp_byp_cn58xx {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_13_63:51;

		uint64_t pctl:5;

		uint64_t reserved_5_7:3;

		uint64_t nctl:5;

#else

		uint64_t nctl:5;

		uint64_t reserved_5_7:3;

		uint64_t pctl:5;

		uint64_t reserved_13_63:51;

#endif

	} cn58xx;

	struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1;

};
@@ -439,12 +613,22 @@ union cvmx_asxx_tx_comp_byp { 
union cvmx_asxx_tx_hi_waterx {

	uint64_t u64;

	struct cvmx_asxx_tx_hi_waterx_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_4_63:60;

		uint64_t mark:4;

#else

		uint64_t mark:4;

		uint64_t reserved_4_63:60;

#endif

	} s;

	struct cvmx_asxx_tx_hi_waterx_cn30xx {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_3_63:61;

		uint64_t mark:3;

#else

		uint64_t mark:3;

		uint64_t reserved_3_63:61;

#endif

	} cn30xx;

	struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;

	struct cvmx_asxx_tx_hi_waterx_s cn38xx;
@@ -457,12 +641,22 @@ union cvmx_asxx_tx_hi_waterx { 
union cvmx_asxx_tx_prt_en {

	uint64_t u64;

	struct cvmx_asxx_tx_prt_en_s {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_4_63:60;

		uint64_t prt_en:4;

#else

		uint64_t prt_en:4;

		uint64_t reserved_4_63:60;

#endif

	} s;

	struct cvmx_asxx_tx_prt_en_cn30xx {

#ifdef __BIG_ENDIAN_BITFIELD

		uint64_t reserved_3_63:61;

		uint64_t prt_en:3;

#else

		uint64_t prt_en:3;

		uint64_t reserved_3_63:61;

#endif

	} cn30xx;

	struct cvmx_asxx_tx_prt_en_cn30xx cn31xx;

	struct cvmx_asxx_tx_prt_en_s cn38xx;

arch/mips/include/asm/octeon/cvmx-ciu-defs.h

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arch/mips/include/asm/octeon/cvmx-ciu2-defs.h

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