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Commit c59a0f15 authored by Atsushi Nemoto's avatar Atsushi Nemoto Committed by Ralf Baechle
Browse files

[MIPS] Remove __flush_icache_page 



__flash_icache_page is unused, so kill it.

Signed-off-by: default avatarAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 1a6183f2

arch/mips/mm/c-r3k.c

+0 −21
Original line number Diff line number Diff line
@@ -268,26 +268,6 @@ static void r3k_flush_data_cache_page(unsigned long addr) 
{

}



static void r3k_flush_icache_page(struct vm_area_struct *vma, struct page *page)

{

	struct mm_struct *mm = vma->vm_mm;

	unsigned long physpage;



	if (cpu_context(smp_processor_id(), mm) == 0)

		return;



	if (!(vma->vm_flags & VM_EXEC))

		return;



#ifdef DEBUG_CACHE

	printk("cpage[%d,%08lx]", cpu_context(smp_processor_id(), mm), page);

#endif



	physpage = (unsigned long) page_address(page);

	if (physpage)

		r3k_flush_icache_range(physpage, physpage + PAGE_SIZE);

}



static void r3k_flush_cache_sigtramp(unsigned long addr)

{

	unsigned long flags;
@@ -335,7 +315,6 @@ void __init r3k_cache_init(void) 
	flush_cache_mm = r3k_flush_cache_mm;

	flush_cache_range = r3k_flush_cache_range;

	flush_cache_page = r3k_flush_cache_page;

	__flush_icache_page = r3k_flush_icache_page;

	flush_icache_range = r3k_flush_icache_range;



	flush_cache_sigtramp = r3k_flush_cache_sigtramp;

arch/mips/mm/c-r4k.c

+0 −77
Original line number Diff line number Diff line
@@ -551,82 +551,6 @@ static void r4k_flush_icache_range(unsigned long start, unsigned long end) 
	instruction_hazard();

}



/*

 * Ok, this seriously sucks.  We use them to flush a user page but don't

 * know the virtual address, so we have to blast away the whole icache

 * which is significantly more expensive than the real thing.  Otoh we at

 * least know the kernel address of the page so we can flush it

 * selectivly.

 */



struct flush_icache_page_args {

	struct vm_area_struct *vma;

	struct page *page;

};



static inline void local_r4k_flush_icache_page(void *args)

{

	struct flush_icache_page_args *fip_args = args;

	struct vm_area_struct *vma = fip_args->vma;

	struct page *page = fip_args->page;



	/*

	 * Tricky ...  Because we don't know the virtual address we've got the

	 * choice of either invalidating the entire primary and secondary

	 * caches or invalidating the secondary caches also.  With the subset

	 * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the

	 * secondary cache will result in any entries in the primary caches

	 * also getting invalidated which hopefully is a bit more economical.

	 */

	if (cpu_has_inclusive_pcaches) {

		unsigned long addr = (unsigned long) page_address(page);



		r4k_blast_scache_page(addr);

		ClearPageDcacheDirty(page);



		return;

	}



	if (!cpu_has_ic_fills_f_dc) {

		unsigned long addr = (unsigned long) page_address(page);

		r4k_blast_dcache_page(addr);

		if (!cpu_icache_snoops_remote_store)

			r4k_blast_scache_page(addr);

		ClearPageDcacheDirty(page);

	}



	/*

	 * We're not sure of the virtual address(es) involved here, so

	 * we have to flush the entire I-cache.

	 */

	if (cpu_has_vtag_icache && vma->vm_mm == current->active_mm) {

		int cpu = smp_processor_id();



		if (cpu_context(cpu, vma->vm_mm) != 0)

			drop_mmu_context(vma->vm_mm, cpu);

	} else

		r4k_blast_icache();

}



static void r4k_flush_icache_page(struct vm_area_struct *vma,

	struct page *page)

{

	struct flush_icache_page_args args;



	/*

	 * If there's no context yet, or the page isn't executable, no I-cache

	 * flush is needed.

	 */

	if (!(vma->vm_flags & VM_EXEC))

		return;



	args.vma = vma;

	args.page = page;



	r4k_on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1);

}





#ifdef CONFIG_DMA_NONCOHERENT



static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
@@ -1291,7 +1215,6 @@ void __init r4k_cache_init(void) 
	__flush_cache_all	= r4k___flush_cache_all;

	flush_cache_mm		= r4k_flush_cache_mm;

	flush_cache_page	= r4k_flush_cache_page;

	__flush_icache_page	= r4k_flush_icache_page;

	flush_cache_range	= r4k_flush_cache_range;



	flush_cache_sigtramp	= r4k_flush_cache_sigtramp;

arch/mips/mm/c-sb1.c

+0 −61
Original line number Diff line number Diff line
@@ -306,66 +306,6 @@ void sb1_flush_icache_range(unsigned long start, unsigned long end) 
	__attribute__((alias("local_sb1_flush_icache_range")));

#endif



/*

 * Flush the icache for a given physical page.  Need to writeback the

 * dcache first, then invalidate the icache.  If the page isn't

 * executable, nothing is required.

 */

static void local_sb1_flush_icache_page(struct vm_area_struct *vma,

	struct page *page)

{

	unsigned long start;

	int cpu = smp_processor_id();



#ifndef CONFIG_SMP

	if (!(vma->vm_flags & VM_EXEC))

		return;

#endif



	/* Need to writeback any dirty data for that page, we have the PA */

	start = (unsigned long)(page-mem_map) << PAGE_SHIFT;

	__sb1_writeback_inv_dcache_phys_range(start, start + PAGE_SIZE);

	/*

	 * If there's a context, bump the ASID (cheaper than a flush,

	 * since we don't know VAs!)

	 */

	if (vma->vm_mm == current->active_mm) {

		if (cpu_context(cpu, vma->vm_mm) != 0)

			drop_mmu_context(vma->vm_mm, cpu);

	} else

		__sb1_flush_icache_range(start, start + PAGE_SIZE);



}



#ifdef CONFIG_SMP

struct flush_icache_page_args {

	struct vm_area_struct *vma;

	struct page *page;

};



static void sb1_flush_icache_page_ipi(void *info)

{

	struct flush_icache_page_args *args = info;

	local_sb1_flush_icache_page(args->vma, args->page);

}



/* Dirty dcache could be on another CPU, so do the IPIs */

static void sb1_flush_icache_page(struct vm_area_struct *vma,

	struct page *page)

{

	struct flush_icache_page_args args;



	if (!(vma->vm_flags & VM_EXEC))

		return;

	args.vma = vma;

	args.page = page;

	on_each_cpu(sb1_flush_icache_page_ipi, (void *) &args, 1, 1);

}

#else

void sb1_flush_icache_page(struct vm_area_struct *vma, struct page *page)

	__attribute__((alias("local_sb1_flush_icache_page")));

#endif



/*

 * A signal trampoline must fit into a single cacheline.

 */
@@ -526,7 +466,6 @@ void sb1_cache_init(void) 


	/* These routines are for Icache coherence with the Dcache */

	flush_icache_range = sb1_flush_icache_range;

	__flush_icache_page = sb1_flush_icache_page;

	flush_icache_all = __sb1_flush_icache_all; /* local only */



	/* This implies an Icache flush too, so can't be nop'ed */

arch/mips/mm/c-tx39.c

+0 −29
Original line number Diff line number Diff line
@@ -248,33 +248,6 @@ static void tx39_flush_icache_range(unsigned long start, unsigned long end) 
	}

}



/*

 * Ok, this seriously sucks.  We use them to flush a user page but don't

 * know the virtual address, so we have to blast away the whole icache

 * which is significantly more expensive than the real thing.  Otoh we at

 * least know the kernel address of the page so we can flush it

 * selectivly.

 */

static void tx39_flush_icache_page(struct vm_area_struct *vma, struct page *page)

{

	unsigned long addr;

	/*

	 * If there's no context yet, or the page isn't executable, no icache

	 * flush is needed.

	 */

	if (!(vma->vm_flags & VM_EXEC))

		return;



	addr = (unsigned long) page_address(page);

	tx39_blast_dcache_page(addr);



	/*

	 * We're not sure of the virtual address(es) involved here, so

	 * we have to flush the entire I-cache.

	 */

	tx39_blast_icache();

}



static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)

{

	unsigned long end;
@@ -382,7 +355,6 @@ void __init tx39_cache_init(void) 
		flush_cache_mm		= (void *) tx39h_flush_icache_all;

		flush_cache_range	= (void *) tx39h_flush_icache_all;

		flush_cache_page	= (void *) tx39h_flush_icache_all;

		__flush_icache_page	= (void *) tx39h_flush_icache_all;

		flush_icache_range	= (void *) tx39h_flush_icache_all;



		flush_cache_sigtramp	= (void *) tx39h_flush_icache_all;
@@ -408,7 +380,6 @@ void __init tx39_cache_init(void) 
		flush_cache_mm = tx39_flush_cache_mm;

		flush_cache_range = tx39_flush_cache_range;

		flush_cache_page = tx39_flush_cache_page;

		__flush_icache_page = tx39_flush_icache_page;

		flush_icache_range = tx39_flush_icache_range;



		flush_cache_sigtramp = tx39_flush_cache_sigtramp;

arch/mips/mm/cache.c

+0 −1
Original line number Diff line number Diff line
@@ -25,7 +25,6 @@ void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start, 
void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page,

	unsigned long pfn);

void (*flush_icache_range)(unsigned long start, unsigned long end);

void (*__flush_icache_page)(struct vm_area_struct *vma, struct page *page);



/* MIPS specific cache operations */

void (*flush_cache_sigtramp)(unsigned long addr);