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Commit c57a4cee authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add the CX MISC GPU block on sdm845 and SDM670"

parents befc01a1 e6f73952

Documentation/devicetree/bindings/gpu/adreno.txt

+5 −3
Original line number Diff line number Diff line
@@ -6,8 +6,9 @@ Required properties: 
- label:		A string used as a descriptive name for the device.

- compatible:		Must be "qcom,kgsl-3d0" and "qcom,kgsl-3d"

- reg:			Specifies the register base address and size, the shader memory

			base address and size (if it exists), and the base address and size

			of the CX_DBGC block (if it exists).

			base address and size (if it exists), base address and size

			of the CX_DBGC block (if it exists), and the base address and

			size of the CX_MISC block (if it exists).

- reg-names:		Resource names used for the physical address of device registers

			and shader memory. "kgsl_3d0_reg_memory" gives the physical address

			and length of device registers while "kgsl_3d0_shader_memory" gives
@@ -15,7 +16,8 @@ Required properties: 
			specified, "qfprom_memory" gives the range for the efuse

			registers used for various configuration options. If specified,

			"kgsl_3d0_cx_dbgc_memory" gives the physical address and length

			of the CX DBGC block.

			of the CX DBGC block. If specified, "cx_misc" gives

			the physical address and length of the CX_MISC block.

- interrupts:		Interrupt mapping for GPU IRQ.

- interrupt-names:	String property to describe the name of the interrupt.

- qcom,id:		An integer used as an identification number for the device.

arch/arm64/boot/dts/qcom/sdm670-gpu.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -49,9 +49,11 @@ 
		status = "ok";

		reg =   <0x5000000 0x40000>,

			<0x5061000 0x800>,

			<0x509e000 0x1000>,

			<0x780000 0x6300>;

		reg-names =     "kgsl_3d0_reg_memory",

				"kgsl_3d0_cx_dbgc_memory",

				"cx_misc",

				"qfprom_memory";

		interrupts = <0 300 0>;

		interrupt-names = "kgsl_3d0_irq";

arch/arm64/boot/dts/qcom/sdm845-gpu.dtsi

+4 −2
Original line number Diff line number Diff line
@@ -48,8 +48,10 @@ 
		label = "kgsl-3d0";

		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";

		status = "ok";

		reg = <0x5000000 0x40000>, <0x5061000 0x800>;

		reg-names = "kgsl_3d0_reg_memory", "kgsl_3d0_cx_dbgc_memory";

		reg = <0x5000000 0x40000>, <0x5061000 0x800>,

			<0x509e000 0x1000>;

		reg-names = "kgsl_3d0_reg_memory", "kgsl_3d0_cx_dbgc_memory",

			"cx_misc";

		interrupts = <0 300 0>;

		interrupt-names = "kgsl_3d0_irq";

		qcom,id = <0>;

drivers/gpu/msm/adreno.c

+67 −0
Original line number Diff line number Diff line
@@ -1262,6 +1262,22 @@ static void adreno_cx_dbgc_probe(struct kgsl_device *device) 
		KGSL_DRV_WARN(device, "cx_dbgc ioremap failed\n");

}



static void adreno_cx_misc_probe(struct kgsl_device *device)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct resource *res;



	res = platform_get_resource_byname(device->pdev, IORESOURCE_MEM,

					   "cx_misc");



	if (res == NULL)

		return;



	adreno_dev->cx_misc_len = resource_size(res);

	adreno_dev->cx_misc_virt = devm_ioremap(device->dev,

					res->start, adreno_dev->cx_misc_len);

}



static void adreno_efuse_read_soc_hw_rev(struct adreno_device *adreno_dev)

{

	unsigned int val;
@@ -1382,6 +1398,9 @@ static int adreno_probe(struct platform_device *pdev) 
	/* Probe for the optional CX_DBGC block */

	adreno_cx_dbgc_probe(device);



	/* Probe for the optional CX_MISC block */

	adreno_cx_misc_probe(device);



	/*

	 * qcom,iommu-secure-id is used to identify MMUs that can handle secure

	 * content but that is only part of the story - the GPU also has to be
@@ -3302,6 +3321,54 @@ void adreno_cx_dbgc_regwrite(struct kgsl_device *device, 
	__raw_writel(value, adreno_dev->cx_dbgc_virt + cx_dbgc_offset);

}



void adreno_cx_misc_regread(struct adreno_device *adreno_dev,

	unsigned int offsetwords, unsigned int *value)

{

	unsigned int cx_misc_offset;



	cx_misc_offset = (offsetwords << 2);

	if (!adreno_dev->cx_misc_virt ||

		(cx_misc_offset >= adreno_dev->cx_misc_len))

		return;



	*value = __raw_readl(adreno_dev->cx_misc_virt + cx_misc_offset);



	/*

	 * ensure this read finishes before the next one.

	 * i.e. act like normal readl()

	 */

	rmb();

}



void adreno_cx_misc_regwrite(struct adreno_device *adreno_dev,

	unsigned int offsetwords, unsigned int value)

{

	unsigned int cx_misc_offset;



	cx_misc_offset = (offsetwords << 2);

	if (!adreno_dev->cx_misc_virt ||

		(cx_misc_offset >= adreno_dev->cx_misc_len))

		return;



	/*

	 * ensure previous writes post before this one,

	 * i.e. act like normal writel()

	 */

	wmb();

	__raw_writel(value, adreno_dev->cx_misc_virt + cx_misc_offset);

}



void adreno_cx_misc_regrmw(struct adreno_device *adreno_dev,

		unsigned int offsetwords,

		unsigned int mask, unsigned int bits)

{

	unsigned int val = 0;



	adreno_cx_misc_regread(adreno_dev, offsetwords, &val);

	val &= ~mask;

	adreno_cx_misc_regwrite(adreno_dev, offsetwords, val | bits);

}



/**

 * adreno_waittimestamp - sleep while waiting for the specified timestamp

 * @device - pointer to a KGSL device structure

drivers/gpu/msm/adreno.h

+12 −0
Original line number Diff line number Diff line
@@ -429,6 +429,8 @@ enum gpu_coresight_sources { 
 * @chipid: Chip ID specific to the GPU

 * @gmem_base: Base physical address of GMEM

 * @gmem_size: GMEM size

 * @cx_misc_len: Length of the CX MISC register block

 * @cx_misc_virt: Pointer where the CX MISC block is mapped

 * @gpucore: Pointer to the adreno_gpu_core structure

 * @pfp_fw: Buffer which holds the pfp ucode

 * @pfp_fw_size: Size of pfp ucode buffer
@@ -509,6 +511,8 @@ struct adreno_device { 
	unsigned long cx_dbgc_base;

	unsigned int cx_dbgc_len;

	void __iomem *cx_dbgc_virt;

	unsigned int cx_misc_len;

	void __iomem *cx_misc_virt;

	const struct adreno_gpu_core *gpucore;

	struct adreno_firmware fw[2];

	size_t gpmu_cmds_size;
@@ -1166,6 +1170,14 @@ void adreno_cx_dbgc_regread(struct kgsl_device *adreno_device, 
		unsigned int offsetwords, unsigned int *value);

void adreno_cx_dbgc_regwrite(struct kgsl_device *device,

		unsigned int offsetwords, unsigned int value);

void adreno_cx_misc_regread(struct adreno_device *adreno_dev,

		unsigned int offsetwords, unsigned int *value);

void adreno_cx_misc_regwrite(struct adreno_device *adreno_dev,

		unsigned int offsetwords, unsigned int value);

void adreno_cx_misc_regrmw(struct adreno_device *adreno_dev,

		unsigned int offsetwords,

		unsigned int mask, unsigned int bits);





#define ADRENO_TARGET(_name, _id) \

static inline int adreno_is_##_name(struct adreno_device *adreno_dev) \