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Commit c553138f authored by Johannes Berg's avatar Johannes Berg Committed by Shawn Guo
Browse files

ARM: imx: use endian-safe readl/readw/writel/writew 



Instead of __raw_*, define imx_* to *_relaxed and use those.

Using imx_* was requested by Arnd because *_relaxed tends to
indicate that the code was carefully reviewed to not require
any synchronisation and otherwise be safe, which isn't the
case here with the automatic conversion.

The conversion itself was done using the following spatch
(since that automatically adjusts the coding style unlike
a simple search&replace).

@@
expression E1, E2;
@@
-__raw_writel(E1, E2)
+imx_writel(E1, E2)
@@
expression E1, E2;
@@
-__raw_writew(E1, E2)
+imx_writew(E1, E2)
@@
expression E1;
@@
-__raw_readl(E1)
+imx_readl(E1)
@@
expression E1;
@@
-__raw_readw(E1)
+imx_readw(E1)

Signed-off-by: default avatarJohannes Berg <johannes@sipsolutions.net>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent e914eceb

arch/arm/mach-imx/3ds_debugboard.c

+15 −15
Original line number Diff line number Diff line
@@ -94,8 +94,8 @@ static void mxc_expio_irq_handler(struct irq_desc *desc) 
	/* irq = gpio irq number */

	desc->irq_data.chip->irq_mask(&desc->irq_data);



	imr_val = __raw_readw(brd_io + INTR_MASK_REG);

	int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;

	imr_val = imx_readw(brd_io + INTR_MASK_REG);

	int_valid = imx_readw(brd_io + INTR_STATUS_REG) & ~imr_val;



	expio_irq = 0;

	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
@@ -117,17 +117,17 @@ static void expio_mask_irq(struct irq_data *d) 
	u16 reg;

	u32 expio = d->hwirq;



	reg = __raw_readw(brd_io + INTR_MASK_REG);

	reg = imx_readw(brd_io + INTR_MASK_REG);

	reg |= (1 << expio);

	__raw_writew(reg, brd_io + INTR_MASK_REG);

	imx_writew(reg, brd_io + INTR_MASK_REG);

}



static void expio_ack_irq(struct irq_data *d)

{

	u32 expio = d->hwirq;



	__raw_writew(1 << expio, brd_io + INTR_RESET_REG);

	__raw_writew(0, brd_io + INTR_RESET_REG);

	imx_writew(1 << expio, brd_io + INTR_RESET_REG);

	imx_writew(0, brd_io + INTR_RESET_REG);

	expio_mask_irq(d);

}
@@ -136,9 +136,9 @@ static void expio_unmask_irq(struct irq_data *d) 
	u16 reg;

	u32 expio = d->hwirq;



	reg = __raw_readw(brd_io + INTR_MASK_REG);

	reg = imx_readw(brd_io + INTR_MASK_REG);

	reg &= ~(1 << expio);

	__raw_writew(reg, brd_io + INTR_MASK_REG);

	imx_writew(reg, brd_io + INTR_MASK_REG);

}



static struct irq_chip expio_irq_chip = {
@@ -162,9 +162,9 @@ int __init mxc_expio_init(u32 base, u32 intr_gpio) 
	if (brd_io == NULL)

		return -ENOMEM;



	if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||

	    (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||

	    (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {

	if ((imx_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||

	    (imx_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||

	    (imx_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {

		pr_info("3-Stack Debug board not detected\n");

		iounmap(brd_io);

		brd_io = NULL;
@@ -181,10 +181,10 @@ int __init mxc_expio_init(u32 base, u32 intr_gpio) 
	gpio_direction_input(intr_gpio);



	/* disable the interrupt and clear the status */

	__raw_writew(0, brd_io + INTR_MASK_REG);

	__raw_writew(0xFFFF, brd_io + INTR_RESET_REG);

	__raw_writew(0, brd_io + INTR_RESET_REG);

	__raw_writew(0x1F, brd_io + INTR_MASK_REG);

	imx_writew(0, brd_io + INTR_MASK_REG);

	imx_writew(0xFFFF, brd_io + INTR_RESET_REG);

	imx_writew(0, brd_io + INTR_RESET_REG);

	imx_writew(0x1F, brd_io + INTR_MASK_REG);



	irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());

	WARN_ON(irq_base < 0);

arch/arm/mach-imx/avic.c

+15 −15
Original line number Diff line number Diff line
@@ -66,12 +66,12 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type) 
		return -EINVAL;



	if (irq < AVIC_NUM_IRQS / 2) {

		irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);

		__raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);

		irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);

		imx_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);

	} else {

		irq -= AVIC_NUM_IRQS / 2;

		irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);

		__raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);

		irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);

		imx_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);

	}



	return 0;
@@ -94,8 +94,8 @@ static void avic_irq_suspend(struct irq_data *d) 
	struct irq_chip_type *ct = gc->chip_types;

	int idx = d->hwirq >> 5;



	avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);

	__raw_writel(gc->wake_active, avic_base + ct->regs.mask);

	avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask);

	imx_writel(gc->wake_active, avic_base + ct->regs.mask);

}



static void avic_irq_resume(struct irq_data *d)
@@ -104,7 +104,7 @@ static void avic_irq_resume(struct irq_data *d) 
	struct irq_chip_type *ct = gc->chip_types;

	int idx = d->hwirq >> 5;



	__raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);

	imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);

}



#else
@@ -140,7 +140,7 @@ static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs) 
	u32 nivector;



	do {

		nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16;

		nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16;

		if (nivector == 0xffff)

			break;
@@ -164,16 +164,16 @@ void __init mxc_init_irq(void __iomem *irqbase) 
	/* put the AVIC into the reset value with

	 * all interrupts disabled

	 */

	__raw_writel(0, avic_base + AVIC_INTCNTL);

	__raw_writel(0x1f, avic_base + AVIC_NIMASK);

	imx_writel(0, avic_base + AVIC_INTCNTL);

	imx_writel(0x1f, avic_base + AVIC_NIMASK);



	/* disable all interrupts */

	__raw_writel(0, avic_base + AVIC_INTENABLEH);

	__raw_writel(0, avic_base + AVIC_INTENABLEL);

	imx_writel(0, avic_base + AVIC_INTENABLEH);

	imx_writel(0, avic_base + AVIC_INTENABLEL);



	/* all IRQ no FIQ */

	__raw_writel(0, avic_base + AVIC_INTTYPEH);

	__raw_writel(0, avic_base + AVIC_INTTYPEL);

	imx_writel(0, avic_base + AVIC_INTTYPEH);

	imx_writel(0, avic_base + AVIC_INTTYPEL);



	irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());

	WARN_ON(irq_base < 0);
@@ -188,7 +188,7 @@ void __init mxc_init_irq(void __iomem *irqbase) 


	/* Set default priority value (0) for all IRQ's */

	for (i = 0; i < 8; i++)

		__raw_writel(0, avic_base + AVIC_NIPRIORITY(i));

		imx_writel(0, avic_base + AVIC_NIPRIORITY(i));



	set_handle_irq(avic_handle_irq);

arch/arm/mach-imx/cpu-imx27.c

+1 −2
Original line number Diff line number Diff line
@@ -39,8 +39,7 @@ static int mx27_read_cpu_rev(void) 
	 * the silicon revision very early we read it here to

	 * avoid any further hooks

	*/

	val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR

				+ SYS_CHIP_ID));

	val = imx_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR + SYS_CHIP_ID));



	mx27_cpu_partnumber = (int)((val >> 12) & 0xFFFF);

arch/arm/mach-imx/cpu-imx31.c

+1 −1
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ static int mx31_read_cpu_rev(void) 
	u32 i, srev;



	/* read SREV register from IIM module */

	srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));

	srev = imx_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));

	srev &= 0xff;



	for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)

arch/arm/mach-imx/cpu-imx35.c

+1 −1
Original line number Diff line number Diff line
@@ -20,7 +20,7 @@ static int mx35_read_cpu_rev(void) 
{

	u32 rev;



	rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));

	rev = imx_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));

	switch (rev) {

	case 0x00:

		return IMX_CHIP_REVISION_1_0;