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Commit c528a25a authored by Mathieu Poirier's avatar Mathieu Poirier Committed by Greg Kroah-Hartman
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coresight: etm3x: consolidating initial config 



There is really no point in having two functions to take care
of doing the initial tracer configuration.  As such moving
everything to 'etm_set_default()'.

Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent e1921729

drivers/hwtracing/coresight/coresight-etm3x.c

+14 −23
Original line number Diff line number Diff line
@@ -41,7 +41,6 @@ module_param_named(boot_enable, boot_enable, int, S_IRUGO); 
/* The number of ETM/PTM currently registered */

static int etm_count;

static struct etm_drvdata *etmdrvdata[NR_CPUS];

static void etm_init_default_data(struct etm_config *config);



/*

 * Memory mapped writes to clear os lock are not supported on some processors
@@ -194,6 +193,19 @@ void etm_set_default(struct etm_config *config) 
	if (WARN_ON_ONCE(!config))

		return;



	/*

	 * Taken verbatim from the TRM:

	 *

	 * To trace all memory:

	 *  set bit [24] in register 0x009, the ETMTECR1, to 1

	 *  set all other bits in register 0x009, the ETMTECR1, to 0

	 *  set all bits in register 0x007, the ETMTECR2, to 0

	 *  set register 0x008, the ETMTEEVR, to 0x6F (TRUE).

	 */

	config->enable_ctrl1 = BIT(24);

	config->enable_ctrl2 = 0x0;

	config->enable_event = ETM_HARD_WIRE_RES_A;



	config->trigger_event = ETM_DEFAULT_EVENT_VAL;

	config->enable_event = ETM_HARD_WIRE_RES_A;
@@ -577,27 +589,6 @@ static void etm_init_arch_data(void *info) 
	CS_LOCK(drvdata->base);

}



static void etm_init_default_data(struct etm_config *config)

{

	if (WARN_ON_ONCE(!config))

		return;



	etm_set_default(config);



	/*

	 * Taken verbatim from the TRM:

	 *

	 * To trace all memory:

	 *  set bit [24] in register 0x009, the ETMTECR1, to 1

	 *  set all other bits in register 0x009, the ETMTECR1, to 0

	 *  set all bits in register 0x007, the ETMTECR2, to 0

	 *  set register 0x008, the ETMTEEVR, to 0x6F (TRUE).

	 */

	config->enable_ctrl1 = BIT(24);

	config->enable_ctrl2 = 0x0;

	config->enable_event = ETM_HARD_WIRE_RES_A;

}



static void etm_init_trace_id(struct etm_drvdata *drvdata)

{

	/*
@@ -674,7 +665,7 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) 
	}



	etm_init_trace_id(drvdata);

	etm_init_default_data(&drvdata->config);

	etm_set_default(&drvdata->config);



	desc->type = CORESIGHT_DEV_TYPE_SOURCE;

	desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;