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Commit c52781f2 authored by Deepak Kumar's avatar Deepak Kumar
Browse files

msm: kgsl: Correctly derive DDR stall cycles from GBIF power counters 



GBIF has power counters to count DDR stall cycles for each AXI channel
separately unlike VBIF which has single power counter to count the total
number of DDR stall cycles.

This change fixes the DDR stall cycles calculation from GBIF power
counters by considering stall cycles of all AXI channels.

Change-Id: I31d7354ab903009fe8f13eca5c507485b84fcc1d
Signed-off-by: default avatarDeepak Kumar <dkumar@codeaurora.org>
parent a7376fcc

drivers/gpu/msm/adreno.c

+24 −0
Original line number Diff line number Diff line
@@ -1600,6 +1600,21 @@ static int _adreno_start(struct adreno_device *adreno_dev) 
			}

		}



		if (adreno_has_gbif(adreno_dev)) {

			if (adreno_dev->starved_ram_lo_ch1 == 0) {

				ret = adreno_perfcounter_get(adreno_dev,

					KGSL_PERFCOUNTER_GROUP_VBIF_PWR, 1,

					&adreno_dev->starved_ram_lo_ch1, NULL,

					PERFCOUNTER_FLAG_KERNEL);



				if (ret) {

					KGSL_DRV_ERR(device,

						"Unable to get perf counters for bus DCVS\n");

					adreno_dev->starved_ram_lo_ch1 = 0;

				}

			}

		}



		/* VBIF DDR cycles */

		if (adreno_dev->ram_cycles_lo == 0) {

			ret = adreno_perfcounter_get(adreno_dev,
@@ -1620,6 +1635,7 @@ static int _adreno_start(struct adreno_device *adreno_dev) 
	adreno_dev->busy_data.gpu_busy = 0;

	adreno_dev->busy_data.vbif_ram_cycles = 0;

	adreno_dev->busy_data.vbif_starved_ram = 0;

	adreno_dev->busy_data.vbif_starved_ram_ch1 = 0;



	/* Restore performance counter registers with saved values */

	adreno_perfcounter_restore(adreno_dev);
@@ -2455,6 +2471,7 @@ int adreno_soft_reset(struct kgsl_device *device) 
	adreno_dev->busy_data.gpu_busy = 0;

	adreno_dev->busy_data.vbif_ram_cycles = 0;

	adreno_dev->busy_data.vbif_starved_ram = 0;

	adreno_dev->busy_data.vbif_starved_ram_ch1 = 0;



	/* Set the page table back to the default page table */

	adreno_ringbuffer_set_global(adreno_dev, 0);
@@ -2991,6 +3008,13 @@ static void adreno_power_stats(struct kgsl_device *device, 
				adreno_dev->starved_ram_lo,

				&busy->vbif_starved_ram);



		if (adreno_has_gbif(adreno_dev)) {

			if (adreno_dev->starved_ram_lo_ch1 != 0)

				starved_ram += counter_delta(device,

					adreno_dev->starved_ram_lo_ch1,

					&busy->vbif_starved_ram_ch1);

		}



		stats->ram_time = ram_cycles;

		stats->ram_wait = starved_ram;

	}

drivers/gpu/msm/adreno.h

+6 −1
Original line number Diff line number Diff line
@@ -284,6 +284,7 @@ struct adreno_busy_data { 
	unsigned int gpu_busy;

	unsigned int vbif_ram_cycles;

	unsigned int vbif_starved_ram;

	unsigned int vbif_starved_ram_ch1;

	unsigned int throttle_cycles[ADRENO_GPMU_THROTTLE_COUNTERS];

};
@@ -401,7 +402,10 @@ struct adreno_gpu_core { 
 * @input_work: Work struct for turning on the GPU after a touch event

 * @busy_data: Struct holding GPU VBIF busy stats

 * @ram_cycles_lo: Number of DDR clock cycles for the monitor session

 * @perfctr_pwr_lo: Number of cycles VBIF is stalled by DDR

 * @starved_ram_lo: Number of cycles VBIF/GBIF is stalled by DDR (Only channel 0

 * stall cycles in case of GBIF)

 * @starved_ram_lo_ch1: Number of cycles GBIF is stalled by DDR channel 1

 * @perfctr_pwr_lo: GPU busy cycles

 * @halt: Atomic variable to check whether the GPU is currently halted

 * @pending_irq_refcnt: Atomic variable to keep track of running IRQ handlers

 * @ctx_d_debugfs: Context debugfs node
@@ -459,6 +463,7 @@ struct adreno_device { 
	struct adreno_busy_data busy_data;

	unsigned int ram_cycles_lo;

	unsigned int starved_ram_lo;

	unsigned int starved_ram_lo_ch1;

	unsigned int perfctr_pwr_lo;

	atomic_t halt;

	atomic_t pending_irq_refcnt;