Loading drivers/gpu/drm/msm/sde/sde_hw_ctl.c +8 −9 Original line number Diff line number Diff line Loading @@ -39,7 +39,7 @@ #define CTL_FLUSH_MASK_ROT BIT(27) #define CTL_FLUSH_MASK_CTL BIT(17) #define SDE_REG_RESET_TIMEOUT_COUNT 20 #define SDE_REG_RESET_TIMEOUT_US 2000 static struct sde_ctl_cfg *_ctl_offset(enum sde_ctl ctl, struct sde_mdss_cfg *m, Loading Loading @@ -298,14 +298,13 @@ static inline int sde_hw_ctl_get_bitmask_cdm(struct sde_hw_ctl *ctx, return 0; } static u32 sde_hw_ctl_poll_reset_status(struct sde_hw_ctl *ctx, u32 count) static u32 sde_hw_ctl_poll_reset_status(struct sde_hw_ctl *ctx, u32 timeout_us) { struct sde_hw_blk_reg_map *c = &ctx->hw; ktime_t timeout; u32 status; /* protect to do at least one iteration */ if (!count) count = 1; timeout = ktime_add_us(ktime_get(), timeout_us); /* * it takes around 30us to have mdp finish resetting its ctl path Loading @@ -313,10 +312,10 @@ static u32 sde_hw_ctl_poll_reset_status(struct sde_hw_ctl *ctx, u32 count) */ do { status = SDE_REG_READ(c, CTL_SW_RESET); status &= 0x01; status &= 0x1; if (status) usleep_range(20, 50); } while (status && --count > 0); } while (status && ktime_compare_safe(ktime_get(), timeout) < 0); return status; } Loading @@ -327,7 +326,7 @@ static int sde_hw_ctl_reset_control(struct sde_hw_ctl *ctx) pr_debug("issuing hw ctl reset for ctl:%d\n", ctx->idx); SDE_REG_WRITE(c, CTL_SW_RESET, 0x1); if (sde_hw_ctl_poll_reset_status(ctx, SDE_REG_RESET_TIMEOUT_COUNT)) if (sde_hw_ctl_poll_reset_status(ctx, SDE_REG_RESET_TIMEOUT_US)) return -EINVAL; return 0; Loading @@ -344,7 +343,7 @@ static int sde_hw_ctl_wait_reset_status(struct sde_hw_ctl *ctx) return 0; pr_debug("hw ctl reset is set for ctl:%d\n", ctx->idx); if (sde_hw_ctl_poll_reset_status(ctx, SDE_REG_RESET_TIMEOUT_COUNT)) { if (sde_hw_ctl_poll_reset_status(ctx, SDE_REG_RESET_TIMEOUT_US)) { pr_err("hw recovery is not complete for ctl:%d\n", ctx->idx); return -EINVAL; } Loading Loading
drivers/gpu/drm/msm/sde/sde_hw_ctl.c +8 −9 Original line number Diff line number Diff line Loading @@ -39,7 +39,7 @@ #define CTL_FLUSH_MASK_ROT BIT(27) #define CTL_FLUSH_MASK_CTL BIT(17) #define SDE_REG_RESET_TIMEOUT_COUNT 20 #define SDE_REG_RESET_TIMEOUT_US 2000 static struct sde_ctl_cfg *_ctl_offset(enum sde_ctl ctl, struct sde_mdss_cfg *m, Loading Loading @@ -298,14 +298,13 @@ static inline int sde_hw_ctl_get_bitmask_cdm(struct sde_hw_ctl *ctx, return 0; } static u32 sde_hw_ctl_poll_reset_status(struct sde_hw_ctl *ctx, u32 count) static u32 sde_hw_ctl_poll_reset_status(struct sde_hw_ctl *ctx, u32 timeout_us) { struct sde_hw_blk_reg_map *c = &ctx->hw; ktime_t timeout; u32 status; /* protect to do at least one iteration */ if (!count) count = 1; timeout = ktime_add_us(ktime_get(), timeout_us); /* * it takes around 30us to have mdp finish resetting its ctl path Loading @@ -313,10 +312,10 @@ static u32 sde_hw_ctl_poll_reset_status(struct sde_hw_ctl *ctx, u32 count) */ do { status = SDE_REG_READ(c, CTL_SW_RESET); status &= 0x01; status &= 0x1; if (status) usleep_range(20, 50); } while (status && --count > 0); } while (status && ktime_compare_safe(ktime_get(), timeout) < 0); return status; } Loading @@ -327,7 +326,7 @@ static int sde_hw_ctl_reset_control(struct sde_hw_ctl *ctx) pr_debug("issuing hw ctl reset for ctl:%d\n", ctx->idx); SDE_REG_WRITE(c, CTL_SW_RESET, 0x1); if (sde_hw_ctl_poll_reset_status(ctx, SDE_REG_RESET_TIMEOUT_COUNT)) if (sde_hw_ctl_poll_reset_status(ctx, SDE_REG_RESET_TIMEOUT_US)) return -EINVAL; return 0; Loading @@ -344,7 +343,7 @@ static int sde_hw_ctl_wait_reset_status(struct sde_hw_ctl *ctx) return 0; pr_debug("hw ctl reset is set for ctl:%d\n", ctx->idx); if (sde_hw_ctl_poll_reset_status(ctx, SDE_REG_RESET_TIMEOUT_COUNT)) { if (sde_hw_ctl_poll_reset_status(ctx, SDE_REG_RESET_TIMEOUT_US)) { pr_err("hw recovery is not complete for ctl:%d\n", ctx->idx); return -EINVAL; } Loading