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Commit c50955fd authored by Vicky Wallace's avatar Vicky Wallace
Browse files

clk: qcom: Remove GPU CC RBCPR clock support on SDM845 



The clock is enabled by XBL and it will be gated by HW
when the GFX rail goes retention or power off.

CRs-Fixed: 2051367
Change-Id: I3707c1d1e29f3d47977f6b4354de783e5d8f53a1
Signed-off-by: default avatarVicky Wallace <vwallace@codeaurora.org>
parent ff3d7de3

drivers/clk/qcom/gpucc-sdm845.c

+0 −72
Original line number Diff line number Diff line
@@ -105,20 +105,6 @@ static const char * const gpu_cc_parent_names_1[] = { 
	"core_bi_pll_test_se",

};



static const struct parent_map gpu_cc_parent_map_2[] = {

	{ P_BI_TCXO, 0 },

	{ P_GPLL0_OUT_MAIN, 5 },

	{ P_GPLL0_OUT_MAIN_DIV, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const char * const gpu_cc_parent_names_2[] = {

	"bi_tcxo",

	"gcc_gpu_gpll0_clk_src",

	"gcc_gpu_gpll0_div_clk_src",

	"core_bi_pll_test_se",

};



static struct pll_vco fabia_vco[] = {

	{ 250000000, 2000000000, 0 },

	{ 125000000, 1000000000, 1 },
@@ -232,29 +218,6 @@ static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { 
	},

};



static const struct freq_tbl ftbl_gpu_cc_rbcpr_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	{ }

};



static struct clk_rcg2 gpu_cc_rbcpr_clk_src = {

	.cmd_rcgr = 0x10b0,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = gpu_cc_parent_map_2,

	.freq_tbl = ftbl_gpu_cc_rbcpr_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpu_cc_rbcpr_clk_src",

		.parent_names = gpu_cc_parent_names_2,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP2(

			MIN, 19200000,

			NOMINAL, 50000000),

	},

};



static struct clk_branch gpu_cc_acd_ahb_clk = {

	.halt_reg = 0x1168,

	.halt_check = BRANCH_HALT,
@@ -488,37 +451,6 @@ static struct clk_branch gpu_cc_pll_test_clk = { 
	},

};



static struct clk_branch gpu_cc_rbcpr_ahb_clk = {

	.halt_reg = 0x10f4,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x10f4,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_rbcpr_ahb_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_rbcpr_clk = {

	.halt_reg = 0x10f0,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x10f0,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_rbcpr_clk",

			.parent_names = (const char *[]){

				"gpu_cc_rbcpr_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_regmap *gpu_cc_sdm845_clocks[] = {

	[GPU_CC_ACD_AHB_CLK] = &gpu_cc_acd_ahb_clk.clkr,

	[GPU_CC_ACD_CXO_CLK] = &gpu_cc_acd_cxo_clk.clkr,
@@ -536,9 +468,6 @@ static struct clk_regmap *gpu_cc_sdm845_clocks[] = { 
	[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,

	[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,

	[GPU_CC_PLL_TEST_CLK] = &gpu_cc_pll_test_clk.clkr,

	[GPU_CC_RBCPR_AHB_CLK] = &gpu_cc_rbcpr_ahb_clk.clkr,

	[GPU_CC_RBCPR_CLK] = &gpu_cc_rbcpr_clk.clkr,

	[GPU_CC_RBCPR_CLK_SRC] = &gpu_cc_rbcpr_clk_src.clkr,

};



static struct clk_regmap *gpu_cc_gfx_sdm845_clocks[] = {
@@ -554,7 +483,6 @@ static const struct qcom_reset_map gpu_cc_sdm845_resets[] = { 
	[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 },

	[GPUCC_GPU_CC_GMU_BCR] = { 0x111c },

	[GPUCC_GPU_CC_GX_BCR] = { 0x1008 },

	[GPUCC_GPU_CC_RBCPR_BCR] = { 0x10ac },

	[GPUCC_GPU_CC_SPDM_BCR] = { 0x1110 },

	[GPUCC_GPU_CC_XO_BCR] = { 0x1000 },

};

include/dt-bindings/clock/qcom,gpucc-sdm845.h

+6 −10
Original line number Diff line number Diff line
@@ -40,13 +40,10 @@ 
#define GPU_CC_PLL1_OUT_ODD					22

#define GPU_CC_PLL1_OUT_TEST					23

#define GPU_CC_PLL_TEST_CLK					24

#define GPU_CC_RBCPR_AHB_CLK					25

#define GPU_CC_RBCPR_CLK					26

#define GPU_CC_RBCPR_CLK_SRC					27

#define GPU_CC_SLEEP_CLK					28

#define GPU_CC_GMU_CLK_SRC					29

#define GPU_CC_CX_GFX3D_CLK					30

#define GPU_CC_CX_GFX3D_SLV_CLK					31

#define GPU_CC_SLEEP_CLK					25

#define GPU_CC_GMU_CLK_SRC					26

#define GPU_CC_CX_GFX3D_CLK					27

#define GPU_CC_CX_GFX3D_SLV_CLK					28



/* GPUCC reset clock registers */

#define GPUCC_GPU_CC_ACD_BCR					0
@@ -54,9 +51,8 @@ 
#define GPUCC_GPU_CC_GFX3D_AON_BCR				2

#define GPUCC_GPU_CC_GMU_BCR					3

#define GPUCC_GPU_CC_GX_BCR					4

#define GPUCC_GPU_CC_RBCPR_BCR					5

#define GPUCC_GPU_CC_SPDM_BCR					6

#define GPUCC_GPU_CC_XO_BCR					7

#define GPUCC_GPU_CC_SPDM_BCR					5

#define GPUCC_GPU_CC_XO_BCR					6



/* GFX3D clock registers */

#define GPU_CC_PLL0						0