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Commit c4b762a9 authored by Lingutla Chandrasekhar's avatar Lingutla Chandrasekhar Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Update L1 Cache dump size for sdm670 



Increase Icache and D cache dump sizes to accommodate
pre-decoded information along with data.

Change-Id: I99e79209b993f7a1c1f6dba0cbdd4a44bf435183
Signed-off-by: default avatarLingutla Chandrasekhar <clingutla@codeaurora.org>
parent 3b157650

arch/arm64/boot/dts/qcom/sdm670.dtsi

+24 −24
Original line number Diff line number Diff line
@@ -56,7 +56,7 @@ 
			reg = <0x0 0x0>;

			enable-method = "psci";

			efficiency = <1024>;

			cache-size = <0x8000>;

			cache-size = <0x10000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_0>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
@@ -75,11 +75,11 @@ 
			};

			L1_I_0: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

				qcom,dump-size = <0x12000>;

			};

			L1_D_0: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

				qcom,dump-size = <0xa000>;

			};

			L1_TLB_0: l1-tlb {

				qcom,dump-size = <0x3000>;
@@ -92,7 +92,7 @@ 
			reg = <0x0 0x100>;

			enable-method = "psci";

			efficiency = <1024>;

			cache-size = <0x8000>;

			cache-size = <0x10000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_100>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
@@ -106,11 +106,11 @@ 
			};

			L1_I_100: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

				qcom,dump-size = <0x12000>;

			};

			L1_D_100: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

				qcom,dump-size = <0xa000>;

			};

			L1_TLB_100: l1-tlb {

				qcom,dump-size = <0x3000>;
@@ -123,7 +123,7 @@ 
			reg = <0x0 0x200>;

			enable-method = "psci";

			efficiency = <1024>;

			cache-size = <0x8000>;

			cache-size = <0x10000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_200>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
@@ -137,11 +137,11 @@ 
			};

			L1_I_200: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

				qcom,dump-size = <0x12000>;

			};

			L1_D_200: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

				qcom,dump-size = <0xa000>;

			};

			L1_TLB_200: l1-tlb {

				qcom,dump-size = <0x3000>;
@@ -154,7 +154,7 @@ 
			reg = <0x0 0x300>;

			enable-method = "psci";

			efficiency = <1024>;

			cache-size = <0x8000>;

			cache-size = <0x10000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_300>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
@@ -168,11 +168,11 @@ 
			};

			L1_I_300: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

				qcom,dump-size = <0x12000>;

			};

			L1_D_300: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

				qcom,dump-size = <0xa000>;

			};

			L1_TLB_300: l1-tlb {

				qcom,dump-size = <0x3000>;
@@ -185,7 +185,7 @@ 
			reg = <0x0 0x400>;

			enable-method = "psci";

			efficiency = <1024>;

			cache-size = <0x8000>;

			cache-size = <0x10000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_400>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
@@ -199,11 +199,11 @@ 
			};

			L1_I_400: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

				qcom,dump-size = <0x12000>;

			};

			L1_D_400: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

				qcom,dump-size = <0xa000>;

			};

			L1_TLB_400: l1-tlb {

				qcom,dump-size = <0x3000>;
@@ -216,7 +216,7 @@ 
			reg = <0x0 0x500>;

			enable-method = "psci";

			efficiency = <1024>;

			cache-size = <0x8000>;

			cache-size = <0x10000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_500>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
@@ -230,11 +230,11 @@ 
			};

			L1_I_500: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

				qcom,dump-size = <0x12000>;

			};

			L1_D_500: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

				qcom,dump-size = <0xa000>;

			};

			L1_TLB_500: l1-tlb {

				qcom,dump-size = <0x3000>;
@@ -247,7 +247,7 @@ 
			reg = <0x0 0x600>;

			enable-method = "psci";

			efficiency = <1740>;

			cache-size = <0x10000>;

			cache-size = <0x20000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_600>;

			sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
@@ -261,11 +261,11 @@ 
			};

			L1_I_600: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x12000>;

				qcom,dump-size = <0x24000>;

			};

			L1_D_600: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x12000>;

				qcom,dump-size = <0x14000>;

			};

			L1_TLB_600: l1-tlb {

				qcom,dump-size = <0x3c000>;
@@ -278,7 +278,7 @@ 
			reg = <0x0 0x700>;

			enable-method = "psci";

			efficiency = <1740>;

			cache-size = <0x10000>;

			cache-size = <0x20000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_700>;

			sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
@@ -292,11 +292,11 @@ 
			};

			L1_I_700: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x12000>;

				qcom,dump-size = <0x24000>;

			};

			L1_D_700: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x12000>;

				qcom,dump-size = <0x14000>;

			};

			L1_TLB_700: l1-tlb {

				qcom,dump-size = <0x3c000>;