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Commit c4091d3f authored by Florian Fainelli's avatar Florian Fainelli Committed by Ralf Baechle
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MIPS: BMIPS: do not change interrupt routing depending on boot CPU 



Commit 4df715aa ("MIPS: BMIPS: support booting from physical CPU other
than 0") changed the interupt routing when we are booting from physical
CPU 0, but the settings are actually correct if we are booting from
physical CPU 0 or CPU 1. Revert that specific change.

Signed-off-by: default avatarFlorian Fainelli <florian@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: cernekee@gmail.com
Cc: jogo@openwrt.org
Cc: blogic@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/5622/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent c055629b

arch/mips/kernel/smp-bmips.c

+1 −7
Original line number Diff line number Diff line
@@ -79,15 +79,9 @@ static void __init bmips_smp_setup(void) 
	 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread

	 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output

	 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output

	 *

	 * If booting from TP1, leave the existing CMT interrupt routing

	 * such that TP0 responds to SW1 and TP1 responds to SW0.

	 */

	if (boot_cpu == 0)

	change_c0_brcm_cmt_intr(0xf8018000,

					(0x02 << 27) | (0x03 << 15));

	else

		change_c0_brcm_cmt_intr(0xf8018000, (0x1d << 27));



	/* single core, 2 threads (2 pipelines) */

	max_cpus = 2;