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Commit c38864a7 authored by Tuomas Tynkkynen's avatar Tuomas Tynkkynen Committed by Thierry Reding
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clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend 



Save and restore this register since the LP1 restore assembly routines
fiddle with it. Otherwise the CPU would keep running on PLLX after
resume from suspend even when DFLL was the original clocksource.

Signed-off-by: default avatarTuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: default avatarMikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: default avatarMichael Turquette <mturquette@linaro.org>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 62a8a094

drivers/clk/tegra/clk-tegra124.c

+14 −0
Original line number Diff line number Diff line
@@ -98,6 +98,8 @@ 
#define PMC_PLLM_WB0_OVERRIDE 0x1dc

#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0



#define CCLKG_BURST_POLICY 0x368



#define UTMIP_PLL_CFG2 0x488

#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)

#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
@@ -130,6 +132,8 @@ 
#ifdef CONFIG_PM_SLEEP

static struct cpu_clk_suspend_context {

	u32 clk_csite_src;

	u32 cclkg_burst;

	u32 cclkg_divider;

} tegra124_cpu_clk_sctx;

#endif
@@ -1323,12 +1327,22 @@ static void tegra124_cpu_clock_suspend(void) 
	tegra124_cpu_clk_sctx.clk_csite_src =

				readl(clk_base + CLK_SOURCE_CSITE);

	writel(3 << 30, clk_base + CLK_SOURCE_CSITE);



	tegra124_cpu_clk_sctx.cclkg_burst =

				readl(clk_base + CCLKG_BURST_POLICY);

	tegra124_cpu_clk_sctx.cclkg_divider =

				readl(clk_base + CCLKG_BURST_POLICY + 4);

}



static void tegra124_cpu_clock_resume(void)

{

	writel(tegra124_cpu_clk_sctx.clk_csite_src,

				clk_base + CLK_SOURCE_CSITE);



	writel(tegra124_cpu_clk_sctx.cclkg_burst,

					clk_base + CCLKG_BURST_POLICY);

	writel(tegra124_cpu_clk_sctx.cclkg_divider,

					clk_base + CCLKG_BURST_POLICY + 4);

}

#endif