Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c310c7b2 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

perf/tools: header file sync up 



When building tools/perf/ it rightly complains about a number of .h
files being out of sync.  Fix this up by syncing them properly with the
relevant in-kernel versions.

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 935893a1

tools/arch/arm/include/uapi/asm/kvm.h

+13 −0
Original line number Diff line number Diff line
@@ -84,6 +84,13 @@ struct kvm_regs { 
#define KVM_VGIC_V2_DIST_SIZE		0x1000

#define KVM_VGIC_V2_CPU_SIZE		0x2000



/* Supported VGICv3 address types  */

#define KVM_VGIC_V3_ADDR_TYPE_DIST	2

#define KVM_VGIC_V3_ADDR_TYPE_REDIST	3



#define KVM_VGIC_V3_DIST_SIZE		SZ_64K

#define KVM_VGIC_V3_REDIST_SIZE		(2 * SZ_64K)



#define KVM_ARM_VCPU_POWER_OFF		0 /* CPU is started in OFF state */

#define KVM_ARM_VCPU_PSCI_0_2		1 /* CPU uses PSCI v0.2 */
@@ -166,6 +173,12 @@ struct kvm_arch_memory_slot { 
#define KVM_REG_ARM_VFP_FPINST		0x1009

#define KVM_REG_ARM_VFP_FPINST2		0x100A



/* KVM-as-firmware specific pseudo-registers */

#define KVM_REG_ARM_FW			(0x0014 << KVM_REG_ARM_COPROC_SHIFT)

#define KVM_REG_ARM_FW_REG(r)		(KVM_REG_ARM | KVM_REG_SIZE_U64 | \

					 KVM_REG_ARM_FW | ((r) & 0xffff))

#define KVM_REG_ARM_PSCI_VERSION	KVM_REG_ARM_FW_REG(0)



/* Device Control API: ARM VGIC */

#define KVM_DEV_ARM_VGIC_GRP_ADDR	0

#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS	1

tools/arch/arm64/include/uapi/asm/kvm.h

+6 −0
Original line number Diff line number Diff line
@@ -195,6 +195,12 @@ struct kvm_arch_memory_slot { 
#define KVM_REG_ARM_TIMER_CNT		ARM64_SYS_REG(3, 3, 14, 3, 2)

#define KVM_REG_ARM_TIMER_CVAL		ARM64_SYS_REG(3, 3, 14, 0, 2)



/* KVM-as-firmware specific pseudo-registers */

#define KVM_REG_ARM_FW			(0x0014 << KVM_REG_ARM_COPROC_SHIFT)

#define KVM_REG_ARM_FW_REG(r)		(KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \

					 KVM_REG_ARM_FW | ((r) & 0xffff))

#define KVM_REG_ARM_PSCI_VERSION	KVM_REG_ARM_FW_REG(0)



/* Device Control API: ARM VGIC */

#define KVM_DEV_ARM_VGIC_GRP_ADDR	0

#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS	1

tools/arch/powerpc/include/uapi/asm/kvm.h

+1 −0
Original line number Diff line number Diff line
@@ -596,6 +596,7 @@ struct kvm_get_htab_header { 
#define KVM_REG_PPC_TM_VSCR	(KVM_REG_PPC_TM | KVM_REG_SIZE_U32 | 0x67)

#define KVM_REG_PPC_TM_DSCR	(KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x68)

#define KVM_REG_PPC_TM_TAR	(KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x69)

#define KVM_REG_PPC_TM_XER	(KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x6a)



/* PPC64 eXternal Interrupt Controller Specification */

#define KVM_DEV_XICS_GRP_SOURCES	1	/* 64-bit source attributes */

tools/arch/s390/include/uapi/asm/kvm.h

+4 −1
Original line number Diff line number Diff line
@@ -197,6 +197,7 @@ struct kvm_guest_debug_arch { 
#define KVM_SYNC_VRS    (1UL << 6)

#define KVM_SYNC_RICCB  (1UL << 7)

#define KVM_SYNC_FPRS   (1UL << 8)

#define KVM_SYNC_BPBC	(1UL << 10)

/* definition of registers in kvm_run */

struct kvm_sync_regs {

	__u64 prefix;	/* prefix register */
@@ -217,7 +218,9 @@ struct kvm_sync_regs { 
	};

	__u8  reserved[512];	/* for future vector expansion */

	__u32 fpc;		/* valid on KVM_SYNC_VRS or KVM_SYNC_FPRS */

	__u8 padding[52];	/* riccb needs to be 64byte aligned */

	__u8 bpbc : 1;		/* bp mode */

	__u8 reserved2 : 7;

	__u8 padding1[51];	/* riccb needs to be 64byte aligned */

	__u8 riccb[64];		/* runtime instrumentation controls block */

};

tools/arch/x86/include/asm/cpufeatures.h

+40 −4
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ 
/*

 * Defines x86 CPU feature bits

 */

#define NCAPINTS	18	/* N 32-bit words worth of info */

#define NCAPINTS	19	/* N 32-bit words worth of info */

#define NBUGINTS	1	/* N 32-bit bug flags */



/*
@@ -189,17 +189,32 @@ 


#define X86_FEATURE_CPB		( 7*32+ 2) /* AMD Core Performance Boost */

#define X86_FEATURE_EPB		( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */

#define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 4) /* Effectively INVPCID && CR4.PCIDE=1 */



#define X86_FEATURE_HW_PSTATE	( 7*32+ 8) /* AMD HW-PState */

#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */



#define X86_FEATURE_INTEL_PT	( 7*32+15) /* Intel Processor Trace */

#define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */

#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */

#define X86_FEATURE_RETPOLINE	( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */

#define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */



#define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */

#define X86_FEATURE_SSBD	( 7*32+17) /* Speculative Store Bypass Disable */



#define X86_FEATURE_RSB_CTXSW	( 7*32+19) /* "" Fill RSB on context switches */



/* Because the ALTERNATIVE scheme is for members of the X86_FEATURE club... */

#define X86_FEATURE_KAISER	( 7*32+31) /* CONFIG_PAGE_TABLE_ISOLATION w/o nokaiser */



#define X86_FEATURE_USE_IBPB	( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */

#define X86_FEATURE_USE_IBRS_FW	( 7*32+22) /* "" Use IBRS during runtime firmware calls */

#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */

#define X86_FEATURE_LS_CFG_SSBD	( 7*32+24) /* "" AMD SSBD implementation */

#define X86_FEATURE_IBRS	( 7*32+25) /* Indirect Branch Restricted Speculation */

#define X86_FEATURE_IBPB	( 7*32+26) /* Indirect Branch Prediction Barrier */

#define X86_FEATURE_STIBP	( 7*32+27) /* Single Thread Indirect Branch Predictors */

#define X86_FEATURE_ZEN		( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */





/* Virtualization flags: Linux defined, word 8 */

#define X86_FEATURE_TPR_SHADOW  ( 8*32+ 0) /* Intel TPR Shadow */

#define X86_FEATURE_VNMI        ( 8*32+ 1) /* Intel Virtual NMI */
@@ -231,6 +246,7 @@ 
#define X86_FEATURE_SMAP	( 9*32+20) /* Supervisor Mode Access Prevention */

#define X86_FEATURE_CLFLUSHOPT	( 9*32+23) /* CLFLUSHOPT instruction */

#define X86_FEATURE_CLWB	( 9*32+24) /* CLWB instruction */

#define X86_FEATURE_INTEL_PT	( 9*32+25) /* Intel Processor Trace */

#define X86_FEATURE_AVX512PF	( 9*32+26) /* AVX-512 Prefetch */

#define X86_FEATURE_AVX512ER	( 9*32+27) /* AVX-512 Exponential and Reciprocal */

#define X86_FEATURE_AVX512CD	( 9*32+28) /* AVX-512 Conflict Detection */
@@ -255,6 +271,10 @@ 
/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */

#define X86_FEATURE_CLZERO	(13*32+0) /* CLZERO instruction */

#define X86_FEATURE_IRPERF	(13*32+1) /* Instructions Retired Count */

#define X86_FEATURE_AMD_IBPB	(13*32+12) /* Indirect Branch Prediction Barrier */

#define X86_FEATURE_AMD_IBRS	(13*32+14) /* Indirect Branch Restricted Speculation */

#define X86_FEATURE_AMD_STIBP	(13*32+15) /* Single Thread Indirect Branch Predictors */

#define X86_FEATURE_VIRT_SSBD	(13*32+25) /* Virtualized Speculative Store Bypass Disable */



/* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */

#define X86_FEATURE_DTHERM	(14*32+ 0) /* Digital Thermal Sensor */
@@ -290,6 +310,16 @@ 
#define X86_FEATURE_SUCCOR	(17*32+1) /* Uncorrectable error containment and recovery */

#define X86_FEATURE_SMCA	(17*32+3) /* Scalable MCA */





/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */

#define X86_FEATURE_AVX512_4VNNIW	(18*32+ 2) /* AVX-512 Neural Network Instructions */

#define X86_FEATURE_AVX512_4FMAPS	(18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */

#define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */

#define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */

#define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */

#define X86_FEATURE_ARCH_CAPABILITIES	(18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */

#define X86_FEATURE_SPEC_CTRL_SSBD	(18*32+31) /* "" Speculative Store Bypass Disable */



/*

 * BUG word(s)

 */
@@ -314,4 +344,10 @@ 
#define X86_BUG_NULL_SEG	X86_BUG(10) /* Nulling a selector preserves the base */

#define X86_BUG_SWAPGS_FENCE	X86_BUG(11) /* SWAPGS without input dep on GS */

#define X86_BUG_MONITOR		X86_BUG(12) /* IPI required to wake up remote CPU */

#define X86_BUG_AMD_E400	X86_BUG(13) /* CPU is among the affected by Erratum 400 */

#define X86_BUG_CPU_MELTDOWN	X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */

#define X86_BUG_SPECTRE_V1	X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */

#define X86_BUG_SPECTRE_V2	X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */

#define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* CPU is affected by speculative store bypass attack */



#endif /* _ASM_X86_CPUFEATURES_H */