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Commit c30a53c7 authored by Jiri Pirko's avatar Jiri Pirko Committed by David S. Miller
Browse files

mlxsw: spectrum_buffers: Get max_buff defaults into limits exposed to user 



Although the device supports max_buff magic values 0 and 0xff, these are
not exposed to the user via devlink.
Therefore, adjust the default values to be within configurable range.

Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
Reviewed-by: default avatarIdo Schimmel <idosch@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent bc872506

drivers/net/ethernet/mellanox/mlxsw/reg.h

+4 −0
Original line number Diff line number Diff line
@@ -3566,6 +3566,10 @@ MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 
 */

MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);



/* shared max_buff limits for dynamic threshold for SBCM, SBPM */

#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1

#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14



/* reg_sbcm_max_buff

 * When the pool associated to the port-pg/tclass is configured to

 * static, Maximum buffer size for the limiter configured in cells.

drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c

+14 −14
Original line number Diff line number Diff line
@@ -255,13 +255,13 @@ static int mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp) 


static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_ingress[] = {

	MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(10000), 8, 0),

	MLXSW_SP_SB_CM(0, 0, 0),

	MLXSW_SP_SB_CM(0, 0, 0),

	MLXSW_SP_SB_CM(0, 0, 0),

	MLXSW_SP_SB_CM(0, 0, 0),

	MLXSW_SP_SB_CM(0, 0, 0),

	MLXSW_SP_SB_CM(0, 0, 0),

	MLXSW_SP_SB_CM(0, 0, 0),

	MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),

	MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),

	MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),

	MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),

	MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),

	MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),

	MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),

	MLXSW_SP_SB_CM(0, 0, 0), /* dummy, this PG does not exist */

	MLXSW_SP_SB_CM(MLXSW_SP_BYTES_TO_CELLS(20000), 1, 3),

};
@@ -385,19 +385,19 @@ static int mlxsw_sp_cpu_port_sb_cms_init(struct mlxsw_sp *mlxsw_sp) 
	}



static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms_ingress[] = {

	MLXSW_SP_SB_PM(0, 0xff),

	MLXSW_SP_SB_PM(0, 0),

	MLXSW_SP_SB_PM(0, 0),

	MLXSW_SP_SB_PM(0, 0xff),

	MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX),

	MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),

	MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),

	MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX),

};



#define MLXSW_SP_SB_PMS_INGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_pms_ingress)



static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms_egress[] = {

	MLXSW_SP_SB_PM(0, 7),

	MLXSW_SP_SB_PM(0, 0),

	MLXSW_SP_SB_PM(0, 0),

	MLXSW_SP_SB_PM(0, 0),

	MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),

	MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),

	MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),

};



#define MLXSW_SP_SB_PMS_EGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_pms_egress)