Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c305fd5f authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amdgpu: fix bug that can't enter thermal interrupt for bonaire. 



Set reversed bit to enable/disable thermal interrupt.

Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarJammy Zhou <Jammy.Zhou@amd.com>
parent e1b35f61

drivers/gpu/drm/amd/amdgpu/ci_dpm.c

+4 −4
Original line number Original line Diff line number Diff line
@@ -6569,12 +6569,12 @@ static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev, 
		switch (state) {

		switch (state) {

		case AMDGPU_IRQ_STATE_DISABLE:

		case AMDGPU_IRQ_STATE_DISABLE:

			cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);

			cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);

			cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;

			cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;

			WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);

			WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);

			break;

			break;

		case AMDGPU_IRQ_STATE_ENABLE:

		case AMDGPU_IRQ_STATE_ENABLE:

			cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);

			cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);

			cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;

			cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;

			WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);

			WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);

			break;

			break;

		default:

		default:
@@ -6586,12 +6586,12 @@ static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev, 
		switch (state) {

		switch (state) {

		case AMDGPU_IRQ_STATE_DISABLE:

		case AMDGPU_IRQ_STATE_DISABLE:

			cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);

			cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);

			cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;

			cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;

			WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);

			WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);

			break;

			break;

		case AMDGPU_IRQ_STATE_ENABLE:

		case AMDGPU_IRQ_STATE_ENABLE:

			cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);

			cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);

			cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;

			cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;

			WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);

			WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);

			break;

			break;

		default:

		default: