Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c2fa4f4a authored by Adam Kropelin's avatar Adam Kropelin Committed by Linus Torvalds
Browse files

[PATCH] pciehp: Use dword accessors for PCI_ROM_ADDRESS



PCI_ROM_ADDRESS is a 32 bit register and as such should be accessed
using pci_bus_{read,write}_config_dword(). A recent audit of drivers/
turned up several cases of byte- and word-sized accesses. The harmful
ones were fixed by Linus directly. This patches up one of the remaining
harmless-but-still-wrong cases caught in the dragnet.

Signed-off-by: default avatarAdam Kropelin <akropel1@rochester.rr.com>
Cc: <kristen.c.accardi@intel.com>
Cc: Greg KH <greg@kroah.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent d648daca
Loading
Loading
Loading
Loading
+1 −3
Original line number Diff line number Diff line
@@ -2526,7 +2526,6 @@ configure_new_function(struct controller *ctrl, struct pci_func *func,
	int cloop;
	u8 temp_byte;
	u8 class_code;
	u16 temp_word;
	u32 rc;
	u32 temp_register;
	u32 base;
@@ -2682,8 +2681,7 @@ configure_new_function(struct controller *ctrl, struct pci_func *func,
		}		/* End of base register loop */

		/* disable ROM base Address */
		temp_word = 0x00L;
		rc = pci_bus_write_config_word (pci_bus, devfn, PCI_ROM_ADDRESS, temp_word);
		rc = pci_bus_write_config_dword (pci_bus, devfn, PCI_ROM_ADDRESS, 0x00);

		/* Set HP parameters (Cache Line Size, Latency Timer) */
		rc = pciehprm_set_hpp(ctrl, func, PCI_HEADER_TYPE_NORMAL);