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Commit c24b3114 authored by Haojian Zhuang's avatar Haojian Zhuang
Browse files

ARM: mmp: support DT in irq 



Merge irq-pxa168 and irq-mmp2. And support device tree also.

Since CONFIG_SPARSE_IRQ is enabled in arch-mmp, base irq starts from
NR_IRQS_LEGACY.

Signed-off-by: default avatarHaojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 3f4dd322

arch/arm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -632,6 +632,7 @@ config ARCH_MMP 
	select CLKDEV_LOOKUP

	select GENERIC_CLOCKEVENTS

	select GPIO_PXA

	select IRQ_DOMAIN

	select TICK_ONESHOT

	select PLAT_PXA

	select SPARSE_IRQ

arch/arm/mach-mmp/Makefile

+4 −4
Original line number Diff line number Diff line
@@ -2,12 +2,12 @@ 
# Makefile for Marvell's PXA168 processors line

#



obj-y				+= common.o clock.o devices.o time.o

obj-y				+= common.o clock.o devices.o time.o irq.o



# SoC support

obj-$(CONFIG_CPU_PXA168)	+= pxa168.o irq-pxa168.o

obj-$(CONFIG_CPU_PXA910)	+= pxa910.o irq-pxa168.o

obj-$(CONFIG_CPU_MMP2)		+= mmp2.o irq-mmp2.o sram.o

obj-$(CONFIG_CPU_PXA168)	+= pxa168.o

obj-$(CONFIG_CPU_PXA910)	+= pxa910.o

obj-$(CONFIG_CPU_MMP2)		+= mmp2.o sram.o



# board support

obj-$(CONFIG_MACH_ASPENITE)	+= aspenite.o

arch/arm/mach-mmp/include/mach/entry-macro.S

+3 −1
Original line number Diff line number Diff line
@@ -6,13 +6,15 @@ 
 * published by the Free Software Foundation.

 */



#include <asm/irq.h>

#include <mach/regs-icu.h>



	.macro	get_irqnr_preamble, base, tmp

	mrc	p15, 0, \tmp, c0, c0, 0		@ CPUID

	and	\tmp, \tmp, #0xff00

	cmp	\tmp, #0x5800

	ldr	\base, =ICU_VIRT_BASE

	ldr	\base, =mmp_icu_base

	ldr	\base, [\base, #0]

	addne	\base, \base, #0x10c		@ PJ1 AP INT SEL register

	addeq	\base, \base, #0x104		@ PJ4 IRQ SEL register

	.endm

arch/arm/mach-mmp/include/mach/irqs.h

+19 −8
Original line number Diff line number Diff line
@@ -125,7 +125,7 @@ 
#define IRQ_MMP2_RTC_MUX		5

#define IRQ_MMP2_TWSI1			7

#define IRQ_MMP2_GPU			8

#define IRQ_MMP2_KEYPAD			9

#define IRQ_MMP2_KEYPAD_MUX		9

#define IRQ_MMP2_ROTARY			10

#define IRQ_MMP2_TRACKBALL		11

#define IRQ_MMP2_ONEWIRE		12
@@ -163,11 +163,11 @@ 
#define IRQ_MMP2_DMA_FIQ		47

#define IRQ_MMP2_DMA_RIQ		48

#define IRQ_MMP2_GPIO			49

#define IRQ_MMP2_SSP_MUX		51

#define IRQ_MMP2_MIPI_HSI1_MUX		51

#define IRQ_MMP2_MMC2			52

#define IRQ_MMP2_MMC3			53

#define IRQ_MMP2_MMC4			54

#define IRQ_MMP2_MIPI_HSI		55

#define IRQ_MMP2_MIPI_HSI0_MUX		55

#define IRQ_MMP2_MSP			58

#define IRQ_MMP2_MIPI_SLIM_DMA		59

#define IRQ_MMP2_PJ4_FREQ_CHG		60
@@ -186,8 +186,14 @@ 
#define IRQ_MMP2_RTC_ALARM		(IRQ_MMP2_RTC_BASE + 0)

#define IRQ_MMP2_RTC			(IRQ_MMP2_RTC_BASE + 1)



/* secondary interrupt of INT #9 */

#define IRQ_MMP2_KEYPAD_BASE		(IRQ_MMP2_RTC_BASE + 2)

#define IRQ_MMP2_KPC			(IRQ_MMP2_KEYPAD_BASE + 0)

#define IRQ_MMP2_ROTORY			(IRQ_MMP2_KEYPAD_BASE + 1)

#define IRQ_MMP2_TBALL			(IRQ_MMP2_KEYPAD_BASE + 2)



/* secondary interrupt of INT #17 */

#define IRQ_MMP2_TWSI_BASE		(IRQ_MMP2_RTC_BASE + 2)

#define IRQ_MMP2_TWSI_BASE		(IRQ_MMP2_KEYPAD_BASE + 3)

#define IRQ_MMP2_TWSI2			(IRQ_MMP2_TWSI_BASE + 0)

#define IRQ_MMP2_TWSI3			(IRQ_MMP2_TWSI_BASE + 1)

#define IRQ_MMP2_TWSI4			(IRQ_MMP2_TWSI_BASE + 2)
@@ -212,11 +218,16 @@ 
#define IRQ_MMP2_COMMRX			(IRQ_MMP2_MISC_BASE + 14)



/* secondary interrupt of INT #51 */

#define IRQ_MMP2_SSP_BASE		(IRQ_MMP2_MISC_BASE + 15)

#define IRQ_MMP2_SSP1_SRDY		(IRQ_MMP2_SSP_BASE + 0)

#define IRQ_MMP2_SSP3_SRDY		(IRQ_MMP2_SSP_BASE + 1)

#define IRQ_MMP2_MIPI_HSI1_BASE		(IRQ_MMP2_MISC_BASE + 15)

#define IRQ_MMP2_HSI1_CAWAKE		(IRQ_MMP2_MIPI_HSI1_BASE + 0)

#define IRQ_MMP2_MIPI_HSI_INT1		(IRQ_MMP2_MIPI_HSI1_BASE + 1)



/* secondary interrupt of INT #55 */

#define IRQ_MMP2_MIPI_HSI0_BASE		(IRQ_MMP2_MIPI_HSI1_BASE + 2)

#define IRQ_MMP2_HSI0_CAWAKE		(IRQ_MMP2_MIPI_HSI0_BASE + 0)

#define IRQ_MMP2_MIPI_HSI_INT0		(IRQ_MMP2_MIPI_HSI0_BASE + 1)



#define IRQ_MMP2_MUX_END		(IRQ_MMP2_SSP_BASE + 2)

#define IRQ_MMP2_MUX_END		(IRQ_MMP2_MIPI_HSI0_BASE + 2)



#define IRQ_GPIO_START			128

#define MMP_NR_BUILTIN_GPIO		192

arch/arm/mach-mmp/irq-mmp2.c

deleted100644 → 0
+0 −158
Original line number Diff line number Diff line 
/*

 *  linux/arch/arm/mach-mmp/irq-mmp2.c

 *

 *  Generic IRQ handling, GPIO IRQ demultiplexing, etc.

 *

 *  Author:	Haojian Zhuang <haojian.zhuang@marvell.com>

 *  Copyright:	Marvell International Ltd.

 *

 *  This program is free software; you can redistribute it and/or modify

 *  it under the terms of the GNU General Public License version 2 as

 *  published by the Free Software Foundation.

 */



#include <linux/init.h>

#include <linux/irq.h>

#include <linux/io.h>



#include <mach/irqs.h>

#include <mach/regs-icu.h>

#include <mach/mmp2.h>



#include "common.h"



static void icu_mask_irq(struct irq_data *d)

{

	uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));



	r &= ~ICU_INT_ROUTE_PJ4_IRQ;

	__raw_writel(r, ICU_INT_CONF(d->irq));

}



static void icu_unmask_irq(struct irq_data *d)

{

	uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));



	r |= ICU_INT_ROUTE_PJ4_IRQ;

	__raw_writel(r, ICU_INT_CONF(d->irq));

}



static struct irq_chip icu_irq_chip = {

	.name		= "icu_irq",

	.irq_mask	= icu_mask_irq,

	.irq_mask_ack	= icu_mask_irq,

	.irq_unmask	= icu_unmask_irq,

};



static void pmic_irq_ack(struct irq_data *d)

{

	if (d->irq == IRQ_MMP2_PMIC)

		mmp2_clear_pmic_int();

}



#define SECOND_IRQ_MASK(_name_, irq_base, prefix)			\

static void _name_##_mask_irq(struct irq_data *d)			\

{									\

	uint32_t r;							\

	r = __raw_readl(prefix##_MASK) | (1 << (d->irq - irq_base));	\

	__raw_writel(r, prefix##_MASK);					\

}



#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix)			\

static void _name_##_unmask_irq(struct irq_data *d)			\

{									\

	uint32_t r;							\

	r = __raw_readl(prefix##_MASK) & ~(1 << (d->irq - irq_base));	\

	__raw_writel(r, prefix##_MASK);					\

}



#define SECOND_IRQ_DEMUX(_name_, irq_base, prefix)			\

static void _name_##_irq_demux(unsigned int irq, struct irq_desc *desc)	\

{									\

	unsigned long status, mask, n;					\

	mask = __raw_readl(prefix##_MASK);				\

	while (1) {							\

		status = __raw_readl(prefix##_STATUS) & ~mask;		\

		if (status == 0)					\

			break;						\

		n = find_first_bit(&status, BITS_PER_LONG);		\

		while (n < BITS_PER_LONG) {				\

			generic_handle_irq(irq_base + n);		\

			n = find_next_bit(&status, BITS_PER_LONG, n+1);	\

		}							\

	}								\

}



#define SECOND_IRQ_CHIP(_name_, irq_base, prefix)			\

SECOND_IRQ_MASK(_name_, irq_base, prefix)				\

SECOND_IRQ_UNMASK(_name_, irq_base, prefix)				\

SECOND_IRQ_DEMUX(_name_, irq_base, prefix)				\

static struct irq_chip _name_##_irq_chip = {				\

	.name		= #_name_,					\

	.irq_mask	= _name_##_mask_irq,				\

	.irq_unmask	= _name_##_unmask_irq,				\

}



SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4);

SECOND_IRQ_CHIP(rtc,  IRQ_MMP2_RTC_BASE,  MMP2_ICU_INT5);

SECOND_IRQ_CHIP(twsi, IRQ_MMP2_TWSI_BASE, MMP2_ICU_INT17);

SECOND_IRQ_CHIP(misc, IRQ_MMP2_MISC_BASE, MMP2_ICU_INT35);

SECOND_IRQ_CHIP(ssp,  IRQ_MMP2_SSP_BASE,  MMP2_ICU_INT51);



static void init_mux_irq(struct irq_chip *chip, int start, int num)

{

	int irq;



	for (irq = start; num > 0; irq++, num--) {

		struct irq_data *d = irq_get_irq_data(irq);



		/* mask and clear the IRQ */

		chip->irq_mask(d);

		if (chip->irq_ack)

			chip->irq_ack(d);



		irq_set_chip(irq, chip);

		set_irq_flags(irq, IRQF_VALID);

		irq_set_handler(irq, handle_level_irq);

	}

}



void __init mmp2_init_icu(void)

{

	int irq;



	for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {

		icu_mask_irq(irq_get_irq_data(irq));

		irq_set_chip(irq, &icu_irq_chip);

		set_irq_flags(irq, IRQF_VALID);



		switch (irq) {

		case IRQ_MMP2_PMIC_MUX:

		case IRQ_MMP2_RTC_MUX:

		case IRQ_MMP2_TWSI_MUX:

		case IRQ_MMP2_MISC_MUX:

		case IRQ_MMP2_SSP_MUX:

			break;

		default:

			irq_set_handler(irq, handle_level_irq);

			break;

		}

	}



	/* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register

	 * to be written to clear the interrupt

	 */

	pmic_irq_chip.irq_ack = pmic_irq_ack;



	init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);

	init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);

	init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5);

	init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15);

	init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2);



	irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);

	irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);

	irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);

	irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);

	irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);

}