Merge "mmc: sdhci-msm: Read and use DDR Config property from dt file" (c1f54881) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/devicetree/bindings/mmc/sdhci-msm.txt

+5 −1

Original line number	Diff line number	Diff line
		@@ -86,7 +86,11 @@ Optional Properties:
		contents will not be retained. It is software responsibility to restore the
		SDCC registers before resuming to normal operation.
		- qcom,force-sdhc1-probe: Force probing sdhc1 even if it is not the boot device.

		- qcom,ddr-config: Certain chipsets and platforms require particular settings for
		the RCLK delay DLL configuration register for HS400 mode to work.
		This value can vary between platforms and msms. If a msm/platform
		require a different DLL setting than the default/POR setting for
		HS400 mode, it can be specified using this field.
		In the following, <supply> can be vdd (flash core voltage) or vdd-io (I/O voltage).
		- qcom,<supply>-always-on - specifies whether supply should be kept "on" always.
		- qcom,<supply>-lpm_sup - specifies whether supply can be kept in low power mode (lpm).

+7 −1

Original line number	Diff line number	Diff line
		@@ -968,7 +968,10 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
		* Reprogramming the value in case it might have been modified by
		* bootloaders.
		*/
		if (msm_host->rclk_delay_fix) {
		if (msm_host->pdata->rclk_wa) {
		writel_relaxed(msm_host->pdata->ddr_config, host->ioaddr +
		msm_host_offset->CORE_DDR_CONFIG_2);
		} else if (msm_host->rclk_delay_fix) {
		writel_relaxed(DDR_CONFIG_2_POR_VAL, host->ioaddr +
		msm_host_offset->CORE_DDR_CONFIG_2);
		} else {
		@@ -1991,6 +1994,9 @@ struct sdhci_msm_pltfm_data sdhci_msm_populate_pdata(struct device dev,
		msm_host->regs_restore.is_supported =
		of_property_read_bool(np, "qcom,restore-after-cx-collapse");

		if (!of_property_read_u32(np, "qcom,ddr-config", &pdata->ddr_config))
		pdata->rclk_wa = true;

		return pdata;
		out:
		return NULL;

+2 −0