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Commit c19ba62f authored by Ravikishore Pampana's avatar Ravikishore Pampana Committed by Karthik Anantha Ram
Browse files

msm: camera: isp: Dynamic CSID IRQ Enable support 



Add support to enable the CSID SOF, EOF, SOT, EOT IRQs dynamically
through debugfs. Add support to enable the short, long , cphy packet
capture dynamically. Added debug logs for this events.
Following command is used to provide the debug value
echo "debug_value" > /sys/kernel/debug/camera_ife/ife_csid_debug"
example: echo 0xf > /sys/kernel/debug/camera_ife/ife_csid_debug"

Change-Id: Ie07d5a7ff9727e272383b6ef6bbfdd2098c2aa65
Signed-off-by: default avatarRavikishore Pampana <rpampana@codeaurora.org>
Signed-off-by: default avatarKarthik Anantha Ram <kartanan@codeaurora.org>
parent 65ad3cde

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c

+58 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include <linux/slab.h>

#include <linux/string.h>

#include <linux/uaccess.h>

#include <linux/debugfs.h>

#include <uapi/media/cam_isp.h>

#include "cam_smmu_api.h"

#include "cam_req_mgr_workq.h"
@@ -1727,6 +1728,16 @@ static int cam_ife_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args) 


	cam_tasklet_start(ctx->common.tasklet_info);



	/* set current csid debug information to CSID HW */

	for (i = 0; i < CAM_IFE_CSID_HW_NUM_MAX; i++) {

		if (g_ife_hw_mgr.csid_devices[i])

			rc = g_ife_hw_mgr.csid_devices[i]->hw_ops.process_cmd(

				g_ife_hw_mgr.csid_devices[i]->hw_priv,

				CAM_IFE_CSID_SET_CSID_DEBUG,

				&g_ife_hw_mgr.debug_cfg.csid_debug,

				sizeof(g_ife_hw_mgr.debug_cfg.csid_debug));

	}



	/* INIT IFE Root: do nothing */



	CAM_DBG(CAM_ISP, "INIT IFE CID ... in ctx id:%d",
@@ -3215,6 +3226,51 @@ static int cam_ife_hw_mgr_sort_dev_with_caps( 
	return 0;

}



static int cam_ife_set_csid_debug(void *data, u64 val)

{

	g_ife_hw_mgr.debug_cfg.csid_debug = val;

	CAM_DBG(CAM_ISP, "Set CSID Debug value :%lld", val);

	return 0;

}



static int cam_ife_get_csid_debug(void *data, u64 *val)

{

	*val = g_ife_hw_mgr.debug_cfg.csid_debug;

	CAM_DBG(CAM_ISP, "Get CSID Debug value :%lld",

		g_ife_hw_mgr.debug_cfg.csid_debug);



	return 0;

}



DEFINE_SIMPLE_ATTRIBUTE(cam_ife_csid_debug,

	cam_ife_get_csid_debug,

	cam_ife_set_csid_debug, "%16llu");



static int cam_ife_hw_mgr_debug_register(void)

{

	g_ife_hw_mgr.debug_cfg.dentry = debugfs_create_dir("camera_ife",

		NULL);



	if (!g_ife_hw_mgr.debug_cfg.dentry) {

		CAM_ERR(CAM_ISP, "failed to create dentry");

		return -ENOMEM;

	}



	if (!debugfs_create_file("ife_csid_debug",

		0644,

		g_ife_hw_mgr.debug_cfg.dentry, NULL,

		&cam_ife_csid_debug)) {

		CAM_ERR(CAM_ISP, "failed to create cam_ife_csid_debug");

		goto err;

	}



	return 0;



err:

	debugfs_remove_recursive(g_ife_hw_mgr.debug_cfg.dentry);

	return -ENOMEM;

}



int cam_ife_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf)

{

	int rc = -EFAULT;
@@ -3380,6 +3436,8 @@ int cam_ife_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf) 
	hw_mgr_intf->hw_prepare_update = cam_ife_mgr_prepare_hw_update;

	hw_mgr_intf->hw_config = cam_ife_mgr_config_hw;

	hw_mgr_intf->hw_cmd = cam_ife_mgr_cmd;



	cam_ife_hw_mgr_debug_register();

	CAM_DBG(CAM_ISP, "Exit");



	return 0;

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h

+13 −1
Original line number Diff line number Diff line
@@ -80,6 +80,18 @@ struct ctx_base_info { 
	enum cam_isp_hw_split_id       split_id;

};



/**

 * struct cam_ife_hw_mgr_debug - contain the debug information

 *

 * @dentry:              Debugfs entry

 * @csid_debug:          csid debug information

 *

 */

struct cam_ife_hw_mgr_debug {

	struct dentry                  *dentry;

	uint64_t                        csid_debug;

};



/**

 * struct cam_vfe_hw_mgr_ctx - IFE HW manager Context object

 *
@@ -142,7 +154,6 @@ struct cam_ife_hw_mgr_ctx { 
	uint32_t                        eof_cnt[CAM_IFE_HW_NUM_MAX];

	atomic_t                        overflow_pending;

	uint32_t                        is_rdi_only_context;



};



/**
@@ -176,6 +187,7 @@ struct cam_ife_hw_mgr { 
						CAM_IFE_CSID_HW_NUM_MAX];

	struct cam_vfe_hw_get_hw_cap   ife_dev_caps[CAM_IFE_HW_NUM_MAX];

	struct cam_req_mgr_core_workq  *workq;

	struct cam_ife_hw_mgr_debug     debug_cfg;

};



/**

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid170.h

+9 −1
Original line number Diff line number Diff line
@@ -199,7 +199,7 @@ static struct cam_ife_csid_csi2_rx_reg_offset 
	.csid_csi2_rx_captured_long_pkt_0_addr        = 0x130,

	.csid_csi2_rx_captured_long_pkt_1_addr        = 0x134,

	.csid_csi2_rx_captured_long_pkt_ftr_addr      = 0x138,

	.csid_csi2_rx_captured_cphy_pkt_ftr_addr      = 0x13c,

	.csid_csi2_rx_captured_cphy_pkt_hdr_addr      = 0x13c,

	.csid_csi2_rx_lane0_misr_addr                 = 0x150,

	.csid_csi2_rx_lane1_misr_addr                 = 0x154,

	.csid_csi2_rx_lane2_misr_addr                 = 0x158,
@@ -213,6 +213,14 @@ static struct cam_ife_csid_csi2_rx_reg_offset 
	.csi2_irq_mask_all                            = 0xFFFFFFF,

	.csi2_misr_enable_shift_val                   = 6,

	.csi2_vc_mode_shift_val                       = 2,

	.csi2_capture_long_pkt_en_shift               = 0,

	.csi2_capture_short_pkt_en_shift              = 1,

	.csi2_capture_cphy_pkt_en_shift               = 2,

	.csi2_capture_long_pkt_dt_shift               = 4,

	.csi2_capture_long_pkt_vc_shift               = 10,

	.csi2_capture_short_pkt_vc_shift              = 15,

	.csi2_capture_cphy_pkt_dt_shift               = 20,

	.csi2_capture_cphy_pkt_vc_shift               = 26,

};



static struct cam_ife_csid_csi2_tpg_reg_offset

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c

+212 −42
Original line number Diff line number Diff line
@@ -32,8 +32,6 @@ 
#define CAM_IFE_CSID_TIMEOUT_SLEEP_US                  1000

#define CAM_IFE_CSID_TIMEOUT_ALL_US                    1000000



#define MEASURE_EN                                     0



static int cam_ife_csid_is_ipp_format_supported(

	uint32_t in_format)

{
@@ -198,7 +196,7 @@ static int cam_ife_csid_get_format_rdi( 
	}



	if (rc)

		CAM_ERR(CAM_ISP, "Unsupported format pair in %d out %d\n",

		CAM_ERR(CAM_ISP, "Unsupported format pair in %d out %d",

			in_format, out_format);



	return rc;
@@ -839,7 +837,7 @@ static int cam_ife_csid_path_reserve(struct cam_ife_csid_hw *csid_hw, 
		path_data->start_pixel = reserve->in_port->left_start;

	}



	CAM_DBG(CAM_ISP, "Res %d width %d height %d\n", reserve->res_id,

	CAM_DBG(CAM_ISP, "Res %d width %d height %d", reserve->res_id,

		path_data->width, path_data->height);

	reserve->node_res = res;
@@ -1205,6 +1203,28 @@ static int cam_ife_csid_enable_csi2( 
		CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION |

		CSID_CSI2_RX_ERROR_CPHY_SOT_RECEPTION |

		CSID_CSI2_RX_ERROR_CPHY_PH_CRC;



	/* Enable the interrupt based on csid debug info set */

	if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOT_IRQ)

		val |= CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED |

			CSID_CSI2_RX_INFO_PHY_DL1_SOT_CAPTURED |

			CSID_CSI2_RX_INFO_PHY_DL2_SOT_CAPTURED |

			CSID_CSI2_RX_INFO_PHY_DL3_SOT_CAPTURED;



	if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOT_IRQ)

		val |= CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED |

			CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED |

			CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED |

			CSID_CSI2_RX_INFO_PHY_DL3_EOT_CAPTURED;



	if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE)

		val |= CSID_CSI2_RX_INFO_SHORT_PKT_CAPTURED;



	if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE)

		val |= CSID_CSI2_RX_INFO_LONG_PKT_CAPTURED;

	if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE)

		val |= CSID_CSI2_RX_INFO_CPHY_PKT_HDR_CAPTURED;



	cam_io_w_mb(val, soc_info->reg_map[0].mem_base +

		csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr);
@@ -1352,6 +1372,34 @@ static int cam_ife_csid_init_config_ipp_path( 
	cam_io_w_mb(val, soc_info->reg_map[0].mem_base +

		csid_reg->ipp_reg->csid_ipp_cfg0_addr);



	/* configure the rx packet capture based on csid debug set */

	val = 0;

	if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE)

		val = ((1 <<

			csid_reg->csi2_reg->csi2_capture_short_pkt_en_shift) |

			(path_data->vc <<

			csid_reg->csi2_reg->csi2_capture_short_pkt_vc_shift));



	if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE)

		val |= ((1 <<

			csid_reg->csi2_reg->csi2_capture_long_pkt_en_shift) |

			(path_data->dt <<

			csid_reg->csi2_reg->csi2_capture_long_pkt_dt_shift) |

			(path_data->vc <<

			csid_reg->csi2_reg->csi2_capture_long_pkt_vc_shift));



	if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE)

		val |= ((1 <<

			csid_reg->csi2_reg->csi2_capture_cphy_pkt_en_shift) |

			(path_data->dt <<

			csid_reg->csi2_reg->csi2_capture_cphy_pkt_dt_shift) |

			(path_data->vc <<

			csid_reg->csi2_reg->csi2_capture_cphy_pkt_vc_shift));



	cam_io_w_mb(val, soc_info->reg_map[0].mem_base +

		csid_reg->csi2_reg->csid_csi2_rx_capture_ctrl_addr);

	CAM_DBG(CAM_ISP, "rx capture control value 0x%x", val);



	res->res_state = CAM_ISP_RESOURCE_STATE_INIT_HW;



	return rc;
@@ -1441,6 +1489,12 @@ static int cam_ife_csid_enable_ipp_path( 


	/* Enable the required ipp interrupts */

	val = CSID_PATH_INFO_RST_DONE | CSID_PATH_ERROR_FIFO_OVERFLOW;



	if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)

		val |= CSID_PATH_INFO_INPUT_SOF;

	if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ)

		val |= CSID_PATH_INFO_INPUT_EOF;



	cam_io_w_mb(val, soc_info->reg_map[0].mem_base +

		csid_reg->ipp_reg->csid_ipp_irq_mask_addr);
@@ -1629,21 +1683,35 @@ static int cam_ife_csid_init_config_rdi_path( 
	val = cam_io_r_mb(soc_info->reg_map[0].mem_base +

		csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr);

	val |= (1 << csid_reg->cmn_reg->path_en_shift_val);

#if MEASURE_EN

	val |= 0x2;

	cam_io_w_mb(0x3, soc_info->reg_map[0].mem_base +

		csid_reg->rdi_reg[id]->csid_rdi_format_measure_cfg0_addr);

	cam_io_w_mb(path_data->height << 16 | path_data->width,

		soc_info->reg_map[0].mem_base +

		csid_reg->rdi_reg[id]->csid_rdi_format_measure_cfg1_addr);

	CAM_DBG(CAM_ISP, "measure_cfg1 0x%x offset 0x%x\n",

		path_data->height << 16 | path_data->width,

		csid_reg->rdi_reg[id]->csid_rdi_format_measure_cfg0_addr);



#endif

	cam_io_w_mb(val, soc_info->reg_map[0].mem_base +

		csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr);



	/* configure the rx packet capture based on csid debug set */

	if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE)

		val = ((1 <<

			csid_reg->csi2_reg->csi2_capture_short_pkt_en_shift) |

			(path_data->vc <<

			csid_reg->csi2_reg->csi2_capture_short_pkt_vc_shift));



	if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE)

		val |= ((1 <<

			csid_reg->csi2_reg->csi2_capture_long_pkt_en_shift) |

			(path_data->dt <<

			csid_reg->csi2_reg->csi2_capture_long_pkt_dt_shift) |

			(path_data->vc <<

			csid_reg->csi2_reg->csi2_capture_long_pkt_vc_shift));



	if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE)

		val |= ((1 <<

			csid_reg->csi2_reg->csi2_capture_cphy_pkt_en_shift) |

			(path_data->dt <<

			csid_reg->csi2_reg->csi2_capture_cphy_pkt_dt_shift) |

			(path_data->vc <<

			csid_reg->csi2_reg->csi2_capture_cphy_pkt_vc_shift));

	cam_io_w_mb(val, soc_info->reg_map[0].mem_base +

		csid_reg->csi2_reg->csid_csi2_rx_capture_ctrl_addr);



	res->res_state = CAM_ISP_RESOURCE_STATE_INIT_HW;



	return rc;
@@ -1710,11 +1778,13 @@ static int cam_ife_csid_enable_rdi_path( 
			csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr);



	/* Enable the required RDI interrupts */

	val = CSID_PATH_INFO_RST_DONE |

#if MEASURE_EN

		CSID_PATH_INFO_INPUT_SOF |

#endif

		CSID_PATH_ERROR_FIFO_OVERFLOW;

	val = CSID_PATH_INFO_RST_DONE | CSID_PATH_ERROR_FIFO_OVERFLOW;



	if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)

		val |= CSID_PATH_INFO_INPUT_SOF;

	if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ)

		val |= CSID_PATH_INFO_INPUT_EOF;



	cam_io_w_mb(val, soc_info->reg_map[0].mem_base +

		csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr);
@@ -1846,6 +1916,20 @@ static int cam_ife_csid_get_time_stamp( 


	return 0;

}



static int cam_ife_csid_set_csid_debug(struct cam_ife_csid_hw   *csid_hw,

	void *cmd_args)

{

	uint32_t  *csid_debug;



	csid_debug = (uint32_t  *) cmd_args;

	csid_hw->csid_debug = *csid_debug;

	CAM_DBG(CAM_ISP, "CSID:%d set csid debug value:%d",

		csid_hw->hw_intf->hw_idx, csid_hw->csid_debug);



	return 0;

}



static int cam_ife_csid_res_wait_for_halt(

	struct cam_ife_csid_hw          *csid_hw,

	struct cam_isp_resource_node    *res)
@@ -2389,6 +2473,9 @@ static int cam_ife_csid_process_cmd(void *hw_priv, 
	case CAM_IFE_CSID_CMD_GET_TIME_STAMP:

		rc = cam_ife_csid_get_time_stamp(csid_hw, cmd_args);

		break;

	case CAM_IFE_CSID_SET_CSID_DEBUG:

		rc = cam_ife_csid_set_csid_debug(csid_hw, cmd_args);

		break;

	default:

		CAM_ERR(CAM_ISP, "CSID:%d un supported cmd:%d",

			csid_hw->hw_intf->hw_idx, cmd_type);
@@ -2407,9 +2494,7 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) 
	struct cam_ife_csid_reg_offset  *csid_reg;

	uint32_t i, irq_status_top, irq_status_rx, irq_status_ipp = 0,

		irq_status_rdi[4];

#if MEASURE_EN

	uint32_t val;

#endif



	csid_hw = (struct cam_ife_csid_hw *)data;
@@ -2503,6 +2588,93 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) 
			 csid_hw->hw_intf->hw_idx);

	}



	if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOT_IRQ) {

		if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED) {

			CAM_ERR(CAM_ISP, "CSID:%d PHY_DL0_EOT_CAPTURED",

				csid_hw->hw_intf->hw_idx);

		}

		if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED) {

			CAM_ERR(CAM_ISP, "CSID:%d PHY_DL1_EOT_CAPTURED",

				csid_hw->hw_intf->hw_idx);

		}

		if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED) {

			CAM_ERR(CAM_ISP, "CSID:%d PHY_DL2_EOT_CAPTURED",

				csid_hw->hw_intf->hw_idx);

		}

		if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL3_EOT_CAPTURED) {

			CAM_ERR(CAM_ISP, "CSID:%d PHY_DL3_EOT_CAPTURED",

				csid_hw->hw_intf->hw_idx);

		}

	}



	if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOT_IRQ) {

		if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED) {

			CAM_ERR(CAM_ISP, "CSID:%d PHY_DL0_SOT_CAPTURED",

				csid_hw->hw_intf->hw_idx);

		}

		if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL1_SOT_CAPTURED) {

			CAM_ERR(CAM_ISP, "CSID:%d PHY_DL1_SOT_CAPTURED",

				csid_hw->hw_intf->hw_idx);

		}

		if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL2_SOT_CAPTURED) {

			CAM_ERR(CAM_ISP, "CSID:%d PHY_DL2_SOT_CAPTURED",

				csid_hw->hw_intf->hw_idx);

		}

		if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL3_SOT_CAPTURED) {

			CAM_ERR(CAM_ISP, "CSID:%d PHY_DL3_SOT_CAPTURED",

				csid_hw->hw_intf->hw_idx);

		}

	}



	if ((csid_hw->csid_debug & CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) &&

		(irq_status_rx & CSID_CSI2_RX_INFO_LONG_PKT_CAPTURED)) {

		CAM_ERR(CAM_ISP, "CSID:%d LONG_PKT_CAPTURED",

			csid_hw->hw_intf->hw_idx);

		val = cam_io_r_mb(soc_info->reg_map[0].mem_base +

			csid_reg->csi2_reg->

			csid_csi2_rx_captured_long_pkt_0_addr);

		CAM_ERR(CAM_ISP, "CSID:%d long packet VC :%d DT:%d WC:%d",

			csid_hw->hw_intf->hw_idx,

			(val >> 22), ((val >> 16) & 0x3F), (val & 0xFFFF));

		val = cam_io_r_mb(soc_info->reg_map[0].mem_base +

			csid_reg->csi2_reg->

			csid_csi2_rx_captured_long_pkt_1_addr);

		CAM_ERR(CAM_ISP, "CSID:%d long packet ECC :%d",

			csid_hw->hw_intf->hw_idx, val);

		val = cam_io_r_mb(soc_info->reg_map[0].mem_base +

			csid_reg->csi2_reg->

			csid_csi2_rx_captured_long_pkt_ftr_addr);

		CAM_ERR(CAM_ISP, "CSID:%d long pkt cal CRC:%d expected CRC:%d",

			csid_hw->hw_intf->hw_idx, (val >> 16), (val & 0xFFFF));

	}

	if ((csid_hw->csid_debug & CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) &&

		(irq_status_rx & CSID_CSI2_RX_INFO_SHORT_PKT_CAPTURED)) {

		CAM_ERR(CAM_ISP, "CSID:%d SHORT_PKT_CAPTURED",

			csid_hw->hw_intf->hw_idx);

		val = cam_io_r_mb(soc_info->reg_map[0].mem_base +

			csid_reg->csi2_reg->

			csid_csi2_rx_captured_short_pkt_0_addr);

		CAM_ERR(CAM_ISP, "CSID:%d short pkt VC :%d DT:%d LC:%d",

			csid_hw->hw_intf->hw_idx,

			(val >> 22), ((val >> 16) & 0x1F), (val & 0xFFFF));

		val = cam_io_r_mb(soc_info->reg_map[0].mem_base +

			csid_reg->csi2_reg->

			csid_csi2_rx_captured_short_pkt_1_addr);

		CAM_ERR(CAM_ISP, "CSID:%d short packet ECC :%d", val);

	}



	if ((csid_hw->csid_debug & CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) &&

		(irq_status_rx & CSID_CSI2_RX_INFO_CPHY_PKT_HDR_CAPTURED)) {

		CAM_ERR(CAM_ISP, "CSID:%d CPHY_PKT_HDR_CAPTURED",

			csid_hw->hw_intf->hw_idx);

		val = cam_io_r_mb(soc_info->reg_map[0].mem_base +

			csid_reg->csi2_reg->

			csid_csi2_rx_captured_cphy_pkt_hdr_addr);

		CAM_ERR(CAM_ISP, "CSID:%d cphy packet VC :%d DT:%d WC:%d",

			csid_hw->hw_intf->hw_idx,

			(val >> 22), ((val >> 16) & 0x1F), (val & 0xFFFF));

	}



	/*read the IPP errors */

	if (csid_reg->cmn_reg->no_pix) {

		/* IPP reset done bit */
@@ -2511,14 +2683,15 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) 
			CAM_DBG(CAM_ISP, "CSID IPP reset complete");

			complete(&csid_hw->csid_ipp_complete);

		}

		if (irq_status_ipp & CSID_PATH_INFO_INPUT_SOF)

			CAM_DBG(CAM_ISP, "CSID IPP SOF received");

		if (irq_status_ipp & CSID_PATH_INFO_INPUT_SOL)

			CAM_DBG(CAM_ISP, "CSID IPP SOL received");

		if (irq_status_ipp & CSID_PATH_INFO_INPUT_EOL)

			CAM_DBG(CAM_ISP, "CSID IPP EOL received");

		if (irq_status_ipp & CSID_PATH_INFO_INPUT_EOF)

			CAM_DBG(CAM_ISP, "CSID IPP EOF received");

		if ((irq_status_ipp & CSID_PATH_INFO_INPUT_SOF) &&

			(csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ))

			CAM_ERR(CAM_ISP, "CSID:%d IPP SOF received",

				csid_hw->hw_intf->hw_idx);



		if ((irq_status_ipp & CSID_PATH_INFO_INPUT_EOF) &&

			(csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ))

			CAM_ERR(CAM_ISP, "CSID:%d IPP EOF received",

				csid_hw->hw_intf->hw_idx);



		if (irq_status_ipp & CSID_PATH_INFO_INPUT_EOF)

			complete(&csid_hw->csid_ipp_complete);
@@ -2536,21 +2709,17 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) 
	for (i = 0; i < csid_reg->cmn_reg->no_rdis; i++) {

		if (irq_status_rdi[i] &

			BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) {

			CAM_DBG(CAM_ISP, "CSID rdi%d reset complete", i);

			CAM_DBG(CAM_ISP, "CSID RDI%d reset complete", i);

			complete(&csid_hw->csid_rdin_complete[i]);

		}



		if (irq_status_rdi[i]  & CSID_PATH_INFO_INPUT_SOF) {

			CAM_DBG(CAM_ISP, "CSID RDI SOF received");

#if MEASURE_EN

			val = cam_io_r(soc_info->reg_map[0].mem_base +

				csid_reg->rdi_reg[i]->

				csid_rdi_format_measure0_addr);

			CAM_ERR(CAM_ISP, "measure 0x%x\n", val);

#endif

		}

		if (irq_status_rdi[i]  & CSID_PATH_INFO_INPUT_EOF)

			CAM_DBG(CAM_ISP, "CSID RDI EOF received");

		if ((irq_status_rdi[i] & CSID_PATH_INFO_INPUT_SOF) &&

			(csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ))

			CAM_ERR(CAM_ISP, "CSID RDI:%d SOF received", i);



		if ((irq_status_rdi[i]  & CSID_PATH_INFO_INPUT_EOF) &&

			(csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ))

			CAM_ERR(CAM_ISP, "CSID RDI:%d EOF received", i);



		if (irq_status_rdi[i] & CSID_PATH_INFO_INPUT_EOF)

			complete(&csid_hw->csid_rdin_complete[i]);
@@ -2678,6 +2847,7 @@ int cam_ife_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, 
		ife_csid_hw->rdi_res[i].res_priv = path_data;

	}



	ife_csid_hw->csid_debug = 0;

	return 0;

err:

	if (rc) {

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h

+25 −2
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 
#define CAM_IFE_CSID_RDI_MAX         4



#define CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED    BIT(0)

#define CSID_CSI2_RX_NFO_PHY_DL1_EOT_CAPTURED     BIT(1)

#define CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED    BIT(1)

#define CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED    BIT(2)

#define CSID_CSI2_RX_INFO_PHY_DL3_EOT_CAPTURED    BIT(3)

#define CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED    BIT(4)
@@ -65,6 +65,18 @@ 
#define CSID_PATH_ERROR_PIX_COUNT                 BIT(13)

#define CSID_PATH_ERROR_LINE_COUNT                BIT(14)



/*

 * Debug values enable the corresponding interrupts and debug logs provide

 * necessary information

 */

#define CSID_DEBUG_ENABLE_SOF_IRQ                 BIT(0)

#define CSID_DEBUG_ENABLE_EOF_IRQ                 BIT(1)

#define CSID_DEBUG_ENABLE_SOT_IRQ                 BIT(2)

#define CSID_DEBUG_ENABLE_EOT_IRQ                 BIT(3)

#define CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE       BIT(4)

#define CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE        BIT(5)

#define CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE        BIT(6)



/* enum cam_csid_path_halt_mode select the path halt mode control */

enum cam_csid_path_halt_mode {

	CSID_HALT_MODE_INTERNAL,
@@ -187,7 +199,7 @@ struct cam_ife_csid_csi2_rx_reg_offset { 
	uint32_t csid_csi2_rx_captured_long_pkt_0_addr;

	uint32_t csid_csi2_rx_captured_long_pkt_1_addr;

	uint32_t csid_csi2_rx_captured_long_pkt_ftr_addr;

	uint32_t csid_csi2_rx_captured_cphy_pkt_ftr_addr;

	uint32_t csid_csi2_rx_captured_cphy_pkt_hdr_addr;

	uint32_t csid_csi2_rx_lane0_misr_addr;

	uint32_t csid_csi2_rx_lane1_misr_addr;

	uint32_t csid_csi2_rx_lane2_misr_addr;
@@ -202,6 +214,14 @@ struct cam_ife_csid_csi2_rx_reg_offset { 
	uint32_t csi2_irq_mask_all;

	uint32_t csi2_misr_enable_shift_val;

	uint32_t csi2_vc_mode_shift_val;

	uint32_t csi2_capture_long_pkt_en_shift;

	uint32_t csi2_capture_short_pkt_en_shift;

	uint32_t csi2_capture_cphy_pkt_en_shift;

	uint32_t csi2_capture_long_pkt_dt_shift;

	uint32_t csi2_capture_long_pkt_vc_shift;

	uint32_t csi2_capture_short_pkt_vc_shift;

	uint32_t csi2_capture_cphy_pkt_dt_shift;

	uint32_t csi2_capture_cphy_pkt_vc_shift;

};



struct cam_ife_csid_csi2_tpg_reg_offset {
@@ -403,6 +423,8 @@ struct cam_ife_csid_path_cfg { 
 * @csid_csi2_reset_complete: csi2 reset completion

 * @csid_ipp_reset_complete:  ipp reset completion

 * @csid_rdin_reset_complete: rdi n completion

 * @csid_debug:               csid debug information to enable the SOT, EOT,

 *                            SOF, EOF, measure etc in the csid hw

 *

 */

struct cam_ife_csid_hw {
@@ -422,6 +444,7 @@ struct cam_ife_csid_hw { 
	struct completion                csid_csi2_complete;

	struct completion                csid_ipp_complete;

	struct completion    csid_rdin_complete[CAM_IFE_CSID_RDI_MAX];

	uint64_t                         csid_debug;

};



int cam_ife_csid_hw_probe_init(struct cam_hw_intf  *csid_hw_intf,