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Commit c12d82c6 authored by Sridhar Gujje's avatar Sridhar Gujje
Browse files

Merge commit '8df48570' into msm-4.9.c6 - PC 226 



* commit '8df48570':
  msm: camera: isp: Try IFE-Lite first when acquiring resources
  msm: camera: core: Check context state prior to handle release
  msm: camera: flash: Add torch handling in early PCR
  msm: camera: csiphy: Correct delay when configure device
  msm: camera: isp: Select epoch config based on Hardware
  msm: camera: eeprom: set platform driver data to null
  msm: camera: isp: Handle excess CSID error irq
  msm: camera: lrme: Add handler function to support early PCR
  msm: camera: lrme: Fix the unpack config and add dump function
  msm: camera: Add support for nominal l1 clock

Change-Id: I3b6f3342d9124869c0ac63e71cc16cfb1350f425
Signed-off-by: default avatarSridhar Gujje <sgujje@codeaurora.org>
parents 32df5cfb 8df48570

drivers/media/platform/msm/camera/cam_core/cam_node.c

+15 −5
Original line number Diff line number Diff line
@@ -286,20 +286,30 @@ static int __cam_node_handle_release_dev(struct cam_node *node, 
		return -EINVAL;

	}



	if (ctx->state > CAM_CTX_UNINIT && ctx->state < CAM_CTX_STATE_MAX) {

		rc = cam_context_handle_release_dev(ctx, release);

		if (rc)

		CAM_ERR(CAM_CORE, "context release failed node %s", node->name);

			CAM_ERR(CAM_CORE, "context release failed for node %s",

				node->name);

	} else {

		CAM_WARN(CAM_CORE,

			"node %s context id %u state %d invalid to release hdl",

			node->name, ctx->ctx_id, ctx->state);

		goto destroy_dev_hdl;

	}



	cam_context_putref(ctx);



destroy_dev_hdl:

	rc = cam_destroy_device_hdl(release->dev_handle);

	if (rc)

		CAM_ERR(CAM_CORE, "destroy device handle is failed node %s",

		CAM_ERR(CAM_CORE, "destroy device hdl failed for node %s",

			node->name);



	CAM_DBG(CAM_CORE, "[%s] Release ctx_id=%d, refcount=%d",

		node->name, ctx->ctx_id,

		atomic_read(&(ctx->refcount.refcount)));



	cam_context_putref(ctx);

	return rc;

}

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c

+7 −5
Original line number Diff line number Diff line
@@ -762,6 +762,8 @@ static int cam_ife_hw_mgr_acquire_res_ife_out_pixel( 
			if (!ife_src_res->hw_res[j])

				continue;



			hw_intf = ife_src_res->hw_res[j]->hw_intf;



			if (j == CAM_ISP_HW_SPLIT_LEFT) {

				vfe_acquire.vfe_out.split_id  =

					CAM_ISP_HW_SPLIT_LEFT;
@@ -769,7 +771,7 @@ static int cam_ife_hw_mgr_acquire_res_ife_out_pixel( 
					/*TBD */

					vfe_acquire.vfe_out.is_master     = 1;

					vfe_acquire.vfe_out.dual_slave_core =

						1;

						(hw_intf->hw_idx == 0) ? 1 : 0;

				} else {

					vfe_acquire.vfe_out.is_master   = 0;

					vfe_acquire.vfe_out.dual_slave_core =
@@ -779,10 +781,10 @@ static int cam_ife_hw_mgr_acquire_res_ife_out_pixel( 
				vfe_acquire.vfe_out.split_id  =

					CAM_ISP_HW_SPLIT_RIGHT;

				vfe_acquire.vfe_out.is_master       = 0;

				vfe_acquire.vfe_out.dual_slave_core = 0;

				vfe_acquire.vfe_out.dual_slave_core =

					(hw_intf->hw_idx == 0) ? 1 : 0;

			}



			hw_intf = ife_src_res->hw_res[j]->hw_intf;

			rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv,

				&vfe_acquire,

				sizeof(struct cam_vfe_acquire_args));
@@ -1038,7 +1040,7 @@ static int cam_ife_mgr_acquire_cid_res( 
	}



	/* Acquire Left if not already acquired */

	for (i = 0; i < CAM_IFE_CSID_HW_NUM_MAX; i++) {

	for (i = CAM_IFE_CSID_HW_NUM_MAX - 1; i >= 0; i--) {

		if (!ife_hw_mgr->csid_devices[i])

			continue;
@@ -1054,7 +1056,7 @@ static int cam_ife_mgr_acquire_cid_res( 
		}

	}



	if (i == CAM_IFE_CSID_HW_NUM_MAX || !csid_acquire.node_res) {

	if (i == -1 || !csid_acquire.node_res) {

		CAM_ERR(CAM_ISP, "Can not acquire ife cid resource for path %d",

			csid_path);

		goto put_res;

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c

+33 −0
Original line number Diff line number Diff line
@@ -45,6 +45,9 @@ 
/* Max number of sof irq's triggered in case of SOF freeze */

#define CAM_CSID_IRQ_SOF_DEBUG_CNT_MAX 6



/* Max CSI Rx irq error count threshold value */

#define CAM_IFE_CSID_MAX_IRQ_ERROR_COUNT               100



static int cam_ife_csid_is_ipp_format_supported(

	uint32_t in_format)

{
@@ -423,6 +426,7 @@ static int cam_ife_csid_global_reset(struct cam_ife_csid_hw *csid_hw) 
	if (val != 0)

		CAM_ERR(CAM_ISP, "CSID:%d IRQ value after reset rc = %d",

			csid_hw->hw_intf->hw_idx, val);

	csid_hw->error_irq_count = 0;



	return rc;

}
@@ -1046,6 +1050,7 @@ static int cam_ife_csid_disable_hw(struct cam_ife_csid_hw *csid_hw) 
			csid_hw->hw_intf->hw_idx);



	csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN;

	csid_hw->error_irq_count = 0;

	return rc;

}
@@ -2645,18 +2650,22 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) 
	if (irq_status_rx & CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW) {

		CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 0 over flow",

			 csid_hw->hw_intf->hw_idx);

		csid_hw->error_irq_count++;

	}

	if (irq_status_rx & CSID_CSI2_RX_ERROR_LANE1_FIFO_OVERFLOW) {

		CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 1 over flow",

			 csid_hw->hw_intf->hw_idx);

		csid_hw->error_irq_count++;

	}

	if (irq_status_rx & CSID_CSI2_RX_ERROR_LANE2_FIFO_OVERFLOW) {

		CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 2 over flow",

			 csid_hw->hw_intf->hw_idx);

		csid_hw->error_irq_count++;

	}

	if (irq_status_rx & CSID_CSI2_RX_ERROR_LANE3_FIFO_OVERFLOW) {

		CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 3 over flow",

			 csid_hw->hw_intf->hw_idx);

		csid_hw->error_irq_count++;

	}

	if (irq_status_rx & CSID_CSI2_RX_ERROR_TG_FIFO_OVERFLOW) {

		CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d TG OVER  FLOW",
@@ -2677,6 +2686,7 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) 
	if (irq_status_rx & CSID_CSI2_RX_ERROR_CRC) {

		CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d ERROR_CRC",

			 csid_hw->hw_intf->hw_idx);

		csid_hw->error_irq_count++;

	}

	if (irq_status_rx & CSID_CSI2_RX_ERROR_ECC) {

		CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d ERROR_ECC",
@@ -2689,10 +2699,12 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) 
	if (irq_status_rx & CSID_CSI2_RX_ERROR_STREAM_UNDERFLOW) {

		CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d ERROR_STREAM_UNDERFLOW",

			 csid_hw->hw_intf->hw_idx);

		csid_hw->error_irq_count++;

	}

	if (irq_status_rx & CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME) {

		CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d UNBOUNDED_FRAME",

			 csid_hw->hw_intf->hw_idx);

		csid_hw->error_irq_count++;

	}



	if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOT_IRQ) {
@@ -2858,6 +2870,26 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) 
		csid_hw->irq_debug_cnt = 0;

	}



	if (csid_hw->error_irq_count >

		CAM_IFE_CSID_MAX_IRQ_ERROR_COUNT) {

		/* Mask line overflow, underflow, unbound interrupts */

		val = cam_io_r_mb(soc_info->reg_map[0].mem_base +

			csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr);



		val &=  ~(CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW |

			CSID_CSI2_RX_ERROR_LANE1_FIFO_OVERFLOW |

			CSID_CSI2_RX_ERROR_LANE2_FIFO_OVERFLOW |

			CSID_CSI2_RX_ERROR_LANE3_FIFO_OVERFLOW |

			CSID_CSI2_RX_ERROR_CRC                 |

			CSID_CSI2_RX_ERROR_STREAM_UNDERFLOW    |

			CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME);



		cam_io_w_mb(val, soc_info->reg_map[0].mem_base +

			csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr);

		CAM_WARN(CAM_ISP, "Masked csi rx error interrupts");

		csid_hw->error_irq_count = 0;

	}



	CAM_DBG(CAM_ISP, "IRQ Handling exit");

	return IRQ_HANDLED;

}
@@ -2975,6 +3007,7 @@ int cam_ife_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, 
	}



	ife_csid_hw->csid_debug = 0;

	ife_csid_hw->error_irq_count = 0;

	return 0;

err:

	if (rc) {

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h

+3 −0
Original line number Diff line number Diff line
@@ -438,6 +438,8 @@ struct cam_ife_csid_path_cfg { 
 * @sof_irq_triggered:        Flag is set on receiving event to enable sof irq

 *                            incase of SOF freeze.

 * @irq_debug_cnt:            Counter to track sof irq's when above flag is set.

 * @error_irq_count           Error IRQ count, if continuous error irq comes

 *                            need to stop the CSID and mask interrupts.

 *

 */

struct cam_ife_csid_hw {
@@ -461,6 +463,7 @@ struct cam_ife_csid_hw { 
	uint64_t                         clk_rate;

	bool                             sof_irq_triggered;

	uint32_t                         irq_debug_cnt;

	uint32_t                         error_irq_count;

};



int cam_ife_csid_hw_probe_init(struct cam_hw_intf  *csid_hw_intf,

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c

+45 −9
Original line number Diff line number Diff line
@@ -211,6 +211,8 @@ static int cam_vfe_camif_resource_start( 
	uint32_t                             epoch0_irq_mask;

	uint32_t                             epoch1_irq_mask;

	uint32_t                             computed_epoch_line_cfg;

	uint32_t                             camera_hw_version = 0;

	int                                  rc = 0;



	if (!camif_res) {

		CAM_ERR(CAM_ISP, "Error! Invalid input arguments");
@@ -250,16 +252,50 @@ static int cam_vfe_camif_resource_start( 
		rsrc_data->common_reg->module_ctrl[

		CAM_VFE_TOP_VER2_MODULE_STATS]->cgc_ovd);



	/* get the HW version */

	rc = cam_cpas_get_cpas_hw_version(&camera_hw_version);



	if (rc) {

		CAM_ERR(CAM_ISP, "Couldn't find HW version. rc: %d", rc);

		return rc;

	}



	/* epoch config */

	epoch0_irq_mask = ((rsrc_data->last_line - rsrc_data->first_line) / 2) +

	switch (camera_hw_version) {

	case CAM_CPAS_TITAN_175_V101:

	case CAM_CPAS_TITAN_175_V100:

		epoch0_irq_mask = ((rsrc_data->last_line -

				rsrc_data->first_line) / 2) +

				rsrc_data->first_line;

	epoch1_irq_mask = rsrc_data->reg_data->epoch_line_cfg & 0xFFFF;

	computed_epoch_line_cfg = (epoch0_irq_mask << 16) | epoch1_irq_mask;

		epoch1_irq_mask = rsrc_data->reg_data->epoch_line_cfg &

				0xFFFF;

		computed_epoch_line_cfg = (epoch0_irq_mask << 16) |

				epoch1_irq_mask;

		cam_io_w_mb(computed_epoch_line_cfg,

		rsrc_data->mem_base + rsrc_data->camif_reg->epoch_irq);

	CAM_DBG(CAM_ISP, "first_line:%u last_line:%u epoch_line_cfg: 0x%x",

		rsrc_data->first_line, rsrc_data->last_line,

				rsrc_data->mem_base +

				rsrc_data->camif_reg->epoch_irq);

		CAM_DBG(CAM_ISP, "first_line: %u\n"

				"last_line: %u\n"

				"epoch_line_cfg: 0x%x",

				rsrc_data->first_line,

				rsrc_data->last_line,

				computed_epoch_line_cfg);

		break;

	case CAM_CPAS_TITAN_170_V100:

	case CAM_CPAS_TITAN_170_V110:

	case CAM_CPAS_TITAN_170_V120:

		cam_io_w_mb(rsrc_data->reg_data->epoch_line_cfg,

				rsrc_data->mem_base +

				rsrc_data->camif_reg->epoch_irq);

		break;

	default:

		cam_io_w_mb(rsrc_data->reg_data->epoch_line_cfg,

				rsrc_data->mem_base +

				rsrc_data->camif_reg->epoch_irq);

		CAM_WARN(CAM_ISP, "Hardware version not proper: 0x%x",

				camera_hw_version);

		break;

	}



	camif_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING;