Merge "ARM: dts: msm: Configure LMH DCVSh for sdm670" (c0e20035) · Commits · e / devices / android_kernel_fairphone_FP3

arch/arm64/boot/dts/qcom/sdm670-thermal.dtsi

+16 −0

Original line number	Diff line number	Diff line
		@@ -10,6 +10,22 @@
		* GNU General Public License for more details.
		*/

		&clock_cpucc {
		lmh_dcvs0: qcom,limits-dcvs@0 {
		compatible = "qcom,msm-hw-limits";
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		qcom,affinity = <0>;
		#thermal-sensor-cells = <0>;
		};

		lmh_dcvs1: qcom,limits-dcvs@1 {
		compatible = "qcom,msm-hw-limits";
		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
		qcom,affinity = <1>;
		#thermal-sensor-cells = <0>;
		};
		};

		&soc {
		qmi-tmd-devices {
		compatible = "qcom,qmi_cooling_devices";

arch/arm64/boot/dts/qcom/sdm670.dtsi

+8 −0

Original line number	Diff line number	Diff line
		@@ -53,6 +53,7 @@
		cache-size = <0x8000>;
		cpu-release-addr = <0x0 0x90000000>;
		next-level-cache = <&L2_0>;
		qcom,lmh-dcvs = <&lmh_dcvs0>;
		L2_0: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x20000>;
		@@ -86,6 +87,7 @@
		cache-size = <0x8000>;
		cpu-release-addr = <0x0 0x90000000>;
		next-level-cache = <&L2_100>;
		qcom,lmh-dcvs = <&lmh_dcvs0>;
		L2_100: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x20000>;
		@@ -114,6 +116,7 @@
		cache-size = <0x8000>;
		cpu-release-addr = <0x0 0x90000000>;
		next-level-cache = <&L2_200>;
		qcom,lmh-dcvs = <&lmh_dcvs0>;
		L2_200: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x20000>;
		@@ -142,6 +145,7 @@
		cache-size = <0x8000>;
		cpu-release-addr = <0x0 0x90000000>;
		next-level-cache = <&L2_300>;
		qcom,lmh-dcvs = <&lmh_dcvs0>;
		L2_300: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x20000>;
		@@ -170,6 +174,7 @@
		cache-size = <0x8000>;
		cpu-release-addr = <0x0 0x90000000>;
		next-level-cache = <&L2_400>;
		qcom,lmh-dcvs = <&lmh_dcvs0>;
		L2_400: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x20000>;
		@@ -198,6 +203,7 @@
		cache-size = <0x8000>;
		cpu-release-addr = <0x0 0x90000000>;
		next-level-cache = <&L2_500>;
		qcom,lmh-dcvs = <&lmh_dcvs0>;
		L2_500: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x20000>;
		@@ -226,6 +232,7 @@
		cache-size = <0x10000>;
		cpu-release-addr = <0x0 0x90000000>;
		next-level-cache = <&L2_600>;
		qcom,lmh-dcvs = <&lmh_dcvs1>;
		L2_600: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x40000>;
		@@ -254,6 +261,7 @@
		cache-size = <0x10000>;
		cpu-release-addr = <0x0 0x90000000>;
		next-level-cache = <&L2_700>;
		qcom,lmh-dcvs = <&lmh_dcvs1>;
		L2_700: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x40000>;