ARM: dts: msm: create PCIe0 devicetree and pinctrl node for sdm845 (c0e0a5f0) · Commits · e / devices / android_kernel_fairphone_FP3

arch/arm64/boot/dts/qcom/sdm845-pcie.dtsi

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		/*
		* Copyright (c) 2017, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#include <dt-bindings/clock/qcom,gcc-sdm845.h>

		&soc {
		pcie0: qcom,pcie@0x1c00000 {
		compatible = "qcom,pci-msm";
		cell-index = <0>;

		reg = <0x1c00000 0x2000>,
		<0x1c06000 0x1000>,
		<0x60000000 0xf1d>,
		<0x60000f20 0xa8>,
		<0x60100000 0x100000>,
		<0x60200000 0x100000>,
		<0x60300000 0xd00000>;

		reg-names = "parf", "phy", "dm_core", "elbi",
		"conf", "io", "bars";

		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
		<0x02000000 0x0 0x60300000 0x60300000 0x0 0xd00000>;
		interrupt-parent = <&pcie0>;
		interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
		20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
		36 37>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0xffffffff>;
		interrupt-map = <0 0 0 0 &intc 0 141 0
		0 0 0 1 &intc 0 149 0
		0 0 0 2 &intc 0 150 0
		0 0 0 3 &intc 0 151 0
		0 0 0 4 &intc 0 152 0
		0 0 0 5 &intc 0 140 0
		0 0 0 6 &intc 0 672 0
		0 0 0 7 &intc 0 673 0
		0 0 0 8 &intc 0 674 0
		0 0 0 9 &intc 0 675 0
		0 0 0 10 &intc 0 676 0
		0 0 0 11 &intc 0 677 0
		0 0 0 12 &intc 0 678 0
		0 0 0 13 &intc 0 679 0
		0 0 0 14 &intc 0 680 0
		0 0 0 15 &intc 0 681 0
		0 0 0 16 &intc 0 682 0
		0 0 0 17 &intc 0 683 0
		0 0 0 18 &intc 0 684 0
		0 0 0 19 &intc 0 685 0
		0 0 0 20 &intc 0 686 0
		0 0 0 21 &intc 0 687 0
		0 0 0 22 &intc 0 688 0
		0 0 0 23 &intc 0 689 0
		0 0 0 24 &intc 0 690 0
		0 0 0 25 &intc 0 691 0
		0 0 0 26 &intc 0 692 0
		0 0 0 27 &intc 0 693 0
		0 0 0 28 &intc 0 694 0
		0 0 0 29 &intc 0 695 0
		0 0 0 30 &intc 0 696 0
		0 0 0 31 &intc 0 697 0
		0 0 0 32 &intc 0 698 0
		0 0 0 33 &intc 0 699 0
		0 0 0 34 &intc 0 700 0
		0 0 0 35 &intc 0 701 0
		0 0 0 36 &intc 0 702 0
		0 0 0 37 &intc 0 703 0>;

		interrupt-names = "int_msi", "int_a", "int_b", "int_c",
		"int_d", "int_global_int",
		"msi_0", "msi_1", "msi_2", "msi_3",
		"msi_4", "msi_5", "msi_6", "msi_7",
		"msi_8", "msi_9", "msi_10", "msi_11",
		"msi_12", "msi_13", "msi_14", "msi_15",
		"msi_16", "msi_17", "msi_18", "msi_19",
		"msi_20", "msi_21", "msi_22", "msi_23",
		"msi_24", "msi_25", "msi_26", "msi_27",
		"msi_28", "msi_29", "msi_30", "msi_31";

		qcom,phy-sequence = <0x804 0x01 0x0
		0x034 0x14 0x0
		0x138 0x30 0x0
		0x048 0x07 0x0
		0x15c 0x06 0x0
		0x090 0x01 0x0
		0x088 0x20 0x0
		0x0f0 0x00 0x0
		0x0f8 0x01 0x0
		0x0f4 0xc9 0x0
		0x11c 0xff 0x0
		0x120 0x3f 0x0
		0x164 0x01 0x0
		0x154 0x00 0x0
		0x148 0x0a 0x0
		0x05c 0x19 0x0
		0x038 0x90 0x0
		0x0b0 0x82 0x0
		0x0c0 0x02 0x0
		0x0bc 0xea 0x0
		0x0b8 0xab 0x0
		0x0a0 0x00 0x0
		0x09c 0x0d 0x0
		0x098 0x04 0x0
		0x13c 0x00 0x0
		0x060 0x06 0x0
		0x068 0x16 0x0
		0x070 0x36 0x0
		0x184 0x01 0x0
		0x15c 0x16 0x0
		0x138 0x33 0x0
		0x03c 0x02 0x0
		0x040 0x07 0x0
		0x080 0x04 0x0
		0x0dc 0x00 0x0
		0x0d8 0x3f 0x0
		0x00c 0x09 0x0
		0x010 0x01 0x0
		0x01c 0x40 0x0
		0x020 0x01 0x0
		0x014 0x02 0x0
		0x018 0x00 0x0
		0x024 0x7e 0x0
		0x028 0x15 0x0
		0x244 0x02 0x0
		0x2a4 0x12 0x0
		0x260 0x10 0x0
		0x28c 0x06 0x0
		0x504 0x03 0x0
		0x500 0x1c 0x0
		0x50c 0x14 0x0
		0x4d4 0x0e 0x0
		0x4d8 0x04 0x0
		0x4dc 0x1a 0x0
		0x434 0x4b 0x0
		0x414 0x04 0x0
		0x40c 0x04 0x0
		0x4f8 0x71 0x0
		0x564 0x59 0x0
		0x568 0x59 0x0
		0x4fc 0x80 0x0
		0x51c 0x40 0x0
		0x444 0x71 0x0
		0x43c 0x40 0x0
		0x854 0x04 0x0
		0x62c 0x52 0x0
		0x654 0x50 0x0
		0x65c 0x1a 0x0
		0x660 0x06 0x0
		0x8c8 0x83 0x0
		0x8cc 0x09 0x0
		0x8d0 0xa2 0x0
		0x8d4 0x40 0x0
		0x8c4 0x02 0x0
		0x9ac 0x00 0x0
		0x8a0 0x01 0x0
		0x9e0 0x00 0x0
		0x9dc 0x20 0x0
		0x9a8 0x00 0x0
		0x8a4 0x01 0x0
		0x8a8 0x73 0x0
		0x9d8 0xaa 0x0
		0x9b0 0x03 0x0
		0xa0c 0x0d 0x0
		0x86c 0x00 0x0
		0x644 0x00 0x0
		0x804 0x03 0x0
		0x800 0x00 0x0
		0x808 0x03 0x0>;

		pinctrl-names = "default";
		pinctrl-0 = <&pcie0_clkreq_default
		&pcie0_perst_default
		&pcie0_wake_default>;

		perst-gpio = <&tlmm 35 0>;
		wake-gpio = <&tlmm 37 0>;

		gdsc-vdd-supply = <&pcie_0_gdsc>;
		vreg-1.8-supply = <&pm8998_l26>;
		vreg-0.9-supply = <&pm8998_l1>;
		vreg-cx-supply = <&pm8998_s9_level>;

		qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>;
		qcom,vreg-0.9-voltage-level = <880000 880000 24000>;
		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
		RPMH_REGULATOR_LEVEL_SVS 0>;

		qcom,l1-supported;
		qcom,l1ss-supported;
		qcom,aux-clk-sync;

		qcom,ep-latency = <10>;

		qcom,boot-option = <0x1>;

		linux,pci-domain = <0>;

		qcom,msi-gicm-addr = <0x17a00040>;
		qcom,msi-gicm-base = <0x2c0>;

		qcom,pcie-phy-ver = <0x30>;
		qcom,use-19p2mhz-aux-clk;

		qcom,smmu-sid-base = <0x1c10>;

		iommu-map = <0x100 &apps_smmu 0x1c11 0x1>,
		<0x200 &apps_smmu 0x1c12 0x1>,
		<0x300 &apps_smmu 0x1c13 0x1>,
		<0x400 &apps_smmu 0x1c14 0x1>,
		<0x500 &apps_smmu 0x1c15 0x1>,
		<0x600 &apps_smmu 0x1c16 0x1>,
		<0x700 &apps_smmu 0x1c17 0x1>,
		<0x800 &apps_smmu 0x1c18 0x1>,
		<0x900 &apps_smmu 0x1c19 0x1>,
		<0xa00 &apps_smmu 0x1c1a 0x1>,
		<0xb00 &apps_smmu 0x1c1b 0x1>,
		<0xc00 &apps_smmu 0x1c1c 0x1>,
		<0xd00 &apps_smmu 0x1c1d 0x1>,
		<0xe00 &apps_smmu 0x1c1e 0x1>,
		<0xf00 &apps_smmu 0x1c1f 0x1>;

		qcom,msm-bus,name = "pcie0";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
		<45 512 0 0>,
		<45 512 500 800>;

		clocks = <&clock_gcc GCC_PCIE_0_PIPE_CLK>,
		<&clock_rpmh RPMH_CXO_CLK>,
		<&clock_gcc GCC_PCIE_0_AUX_CLK>,
		<&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>,
		<&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>,
		<&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>,
		<&clock_gcc GCC_PCIE_0_CLKREF_CLK>,
		<&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
		<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
		<&clock_gcc GCC_PCIE_PHY_REFGEN_CLK>,
		<&clock_gcc GCC_PCIE_PHY_AUX_CLK>;

		clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
		"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
		"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
		"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
		"pcie_tbu_clk", "pcie_phy_refgen_clk",
		"pcie_phy_aux_clk";

		max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>,
		<0>, <0>, <0>, <0>, <100000000>, <0>;

		resets = <&clock_gcc GCC_PCIE_0_BCR>,
		<&clock_gcc GCC_PCIE_0_PHY_BCR>;

		reset-names = "pcie_0_core_reset",
		"pcie_0_phy_reset";
		};
		};

arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi

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		@@ -160,6 +160,47 @@
		};
		};

		pcie0 {
		pcie0_clkreq_default: pcie0_clkreq_default {
		mux {
		pins = "gpio36";
		function = "pci_e0";
		};

		config {
		pins = "gpio36";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		pcie0_perst_default: pcie0_perst_default {
		mux {
		pins = "gpio35";
		function = "gpio";
		};

		config {
		pins = "gpio35";
		drive-strength = <2>;
		bias-pull-down;
		};
		};

		pcie0_wake_default: pcie0_wake_default {
		mux {
		pins = "gpio37";
		function = "gpio";
		};

		config {
		pins = "gpio37";
		drive-strength = <2>;
		bias-pull-down;
		};
		};
		};

		cdc_reset_ctrl {
		cdc_reset_sleep: cdc_reset_sleep {
		mux {

arch/arm64/boot/dts/qcom/sdm845.dtsi

+2 −0

Original line number	Diff line number	Diff line
		@@ -34,6 +34,7 @@
		aliases {
		ufshc1 = &ufshc_mem; /* Embedded UFS slot */
		ufshc2 = &ufshc_card; /* Removable UFS slot */
		pci-domain0 = &pcie0;
		sdhc2 = &sdhc_2; /* SDC2 SD card slot */
		};

		@@ -3639,6 +3640,7 @@
		#include "sdm845-vidc.dtsi"
		#include "sdm845-pm.dtsi"
		#include "sdm845-pinctrl.dtsi"
		#include "sdm845-pcie.dtsi"
		#include "sdm845-audio.dtsi"
		#include "sdm845-gpu.dtsi"
		#include "sdm845-usb.dtsi"