Merge "ARM: dts: msm: Add support for CPU clocks for SDM632"

		};

	};

};

&clock_cpu {

	/delete-property/ vdd-cl-supply;

	status = "disabled";

	compatible = "qcom,cpu-clock-sdm632";

	reg =   <0xb114000  0x68>,

		<0xb014000  0x68>,

		<0xb016000  0x8>,

		<0xb116000  0x8>,

		<0xb1d0000  0x8>,

		<0xb011050  0x8>,

		<0xb111050  0x8>,

		<0xb1d1050  0x8>,

		<0x00a412c  0x8>;

	reg-names = "rcgwr-c0-base", "rcgwr-c1-base",

		    "apcs-c1-pll-base", "apcs-c0-pll-base",

		    "apcs-cci-pll-base", "apcs-c1-rcg-base",

		    "apcs-c0-rcg-base", "apcs-cci-rcg-base",

		    "efuse";

	qcom,num-clusters = <2>;

	clocks = <&clock_gcc clk_xo_a_clk_src>;

	clock-names = "xo_a";

	qcom,speed0-bin-v0-c0 =

		<          0 0>,

		<   614400000 1>,

		<   883200000 2>,

		<  1036200000 3>,

		<  1363200000 4>,

		<  1563000000 5>,

		<  1670400000 6>,

		<  1785600000 7>;

	qcom,speed0-bin-v0-c1 =

		<          0 0>,

		<   633600000 1>,

		<   902400000 2>,

		<  1094400000 3>,

		<  1401600000 4>,

		<  1555200000 5>,

		<  1785600000 6>;

	qcom,speed0-bin-v0-cci =

		<          0 0>,

		<  307200000 1>,

		<  403200000 2>,

		<  499200000 3>,

		<  691200000 4>,

		<  768000000 5>,

		<  787200000 6>;

	#clock-cells = <1>;

};

&apc_vreg {

	status = "disabled";

};